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* [PATCH] ppc32: use correct register names in arch/ppc/kernel/relocate_kernel.SOlaf Hering2005-06-30
| | | | | | | | | | | | | CONFIG_KEXEC=y doesnt work: arch/ppc/kernel/relocate_kernel.S:37: Error: unsupported relocation against SRR1 arch/ppc/kernel/relocate_kernel.S:39: Error: unsupported relocation against SRR0 Signed-off-by: Olaf Hering <olh@suse.de> Cc: "Eric W. Biederman" <ebiederm@xmission.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Merge rsync://rsync.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6Linus Torvalds2005-06-30
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| * [IA64] Update zx1_defconfigTony Luck2005-06-29
| | | | | | | | Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64] Update tiger_defconfigTony Luck2005-06-29
| | | | | | | | Signed-off-by: Tony Luck <tony.luck@intel.com>
| * Auto merge with /home/aegl/GIT/linusTony Luck2005-06-29
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| * | [IA64] Fix another IA64 preemption problemPeter Chubb2005-06-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's another problem shown up by Ingo's recent patch to make smp_processor_id() complain if it's called with preemption enabled. local_finish_flush_tlb_mm() calls activate_context() in a situation where it could be rescheduled to another processor. This patch disables preemption around the call. Signed-off-by: Peter Chubb <peterc@gelato.unsw.edu.au> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * | [IA64] Replace stale KDB-code with useful MAGIC_SYSRQ code in simserial.cDavid Mosberger-Tang2005-06-28
| | | | | | | | | | | | | | | | | | | | | | | | Patch makes it possible to use the "F4" function key to do magic sysrq in the HP Ski simulator. Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * | [IA64-SGI] Altix patch to tiocx, add subsys_initcallBruce Losure2005-06-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes an ordering issue between the init code for the tiocx bus driver and tiocx-related device drivers. Also adds a new brick to the list of known FPGA bricks. Signed-off-by: Bruce Losure <blosure@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * | [IA64] sparse cleanup of TIOCA filesPrarit Bhargava2005-06-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is a sparse compile cleanup of tioca_provider.c, sn_hwperf.h, and tioca_provider.h. Each of these files had sparse warnings when compiled. Signed-off-by: Prarit Bhargava <prarit@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * | [IA64-SGI] - new macros for SGI SN simulator Jack Steiner2005-06-28
| | | | | | | | | | | | | | | | | | | | | | | | This patch changes some macros that are used when running kernel on the SGI simulator. Signed-off-by: Jack Steiner <steiner@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * | [IA64] sparse cleanup of shub_mmr.hPrarit Bhargava2005-06-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is a sparse compile cleanup of shub_mmr.h using both the defconfig and the sn2_defconfig config files. The issue with this file was the missing usage of __IA64_UL_CONST wrapper. This wrapper is defined in include/asm-ia64/types.h and wraps a long constant definition with UL or with nothing depending on its usage in the kernel. The missing wrapper caused many sparse compile errors like warning: constant 0x0x0000000010000380 so big it is long Signed-off-by: Prarit Bhargava <prarit@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * | [IA64] Speed up lfetch.fault [NULL]David Mosberger-Tang2005-06-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch greatly speeds up the handling of lfetch.fault instructions which result in NaT consumption. Due to the NaT-page mapped at address 0, this is guaranteed to happen when lfetch.fault'ing a NULL pointer. With this patch in place, we can even define prefetch()/prefetchw() as lfetch.fault without significant performance degradation. More importantly, it allows compilers to be more aggressive with using lfetch.fault on pointers that might be NULL. Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * | [IA64] Recognize HP sx2000 chipsetBjorn Helgaas2005-06-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No functional change, just identify the device nicely: -IOC: Unknown (103c:12ec) 0.1 HPA 0xf8020002000 IOVA space 1024Mb at 0x40000000 +IOC: sx2000 0.1 HPA 0xf8020002000 IOVA space 1024Mb at 0x40000000 We used to create fake PCI devices for these chips, but we no longer do that. So I don't think there's any reason to touch pci_ids.h now. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * | [IA64-SGI] altix: enable vgacon supportMark Maule2005-06-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Altix patch to enable use of vgacon driver on that platform. Depends on the PCDP generalization patch discussed at: http://marc.theaimsgroup.com/?l=linux-ia64&m=111446235101939&w=2 Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * | [IA64-SGI] pcdp: add PCDP pci interface supportMark Maule2005-06-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Resend 2 with changes per Bjorn Helgaas comments. Changes from original: + Change globals to vga_console_iobase/vga_console_membase and make them unconditional. + Address style-related comments. Patch to extend the PCDP vga setup code to support PCI io/mem translations for the legacy vga ioport and ram spaces on architectures (e.g. altix) which need them. Summary of the changes: drivers/firmware/pcdp.c drivers/firmware/pcdp.h ----------------------- + add declaration for the spec-defined PCI interface struct (pcdp_if_pci) as well as support macros. + extend setup_vga_console() to know about pcdp_if_pci and add a couple of globals to hold the io and mem translation offsets if present. arch/ia64/kernel/setup.c ------------------------ + tweek early_console_setup() to allow multiple early console setup routines to be called. include/asm-ia64/vga.h ---------------------- + make VGA_MAP_MEM vga_console_membase aware Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * | Auto merge with /home/aegl/GIT/ia64-testTony Luck2005-06-28
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| | * \ Auto merge with /home/aegl/GIT/linusTony Luck2005-06-15
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| | * \ \ Merge with temp tree to get David's gdb inferior calls patchTony Luck2005-05-17
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| | | * | | [IA64] Fix convert_to_non_syscall() so gdb inferior calls work againDavid Mosberger-Tang2005-05-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix convert_to_non_syscall() so it arranges for the kernel to be left via ia64_leave_kernel() rather than ia64_leave_syscall(). The latter no longer tolerates being called with pSys=0 and pNonSys=1. Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | [IA64] Merge audit fix for fsyscalls with syscall-optimizationsDavid Mosberger-Tang2005-05-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | [IA64] need r29=psr *after* rsm psr.iDavid Mosberger-Tang2005-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Yanmin Zhang pointed out a sequence problem when saving the psr. David Mosberger provided this patch (which gave up a cycle). Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | [IA64] use srlz.d instead of srlz.i in ia64_leave_kernel()David Mosberger-Tang2005-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch switches the srlz.i in ia64_leave_kernel() to srlz.d. As per architecture manual, the former is needed only to ensure that the clearing of PSR.IC is seen by the VHPT for subsequent instruction fetches. However, since the remainder of the code (up to and including the RFI instruction) is mapped by a pinned TLB entry, there is no chance of an iTLB miss and we don't care whether or not the VHPT sees PSR.IC cleared. Since srlz.d is substantially cheaper than srlz.i, this should shave off a few cycles off the interrupt path (unverified though; I'm not setup to measure this at the moment). Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | [IA64] Annotate fsys_bubble_down() with McKinley dispatch info.David Mosberger-Tang2005-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes comments & formatting only. There is no code change. Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | [IA64] Reschedule fsys_bubble_down().David Mosberger-Tang2005-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improvements come from eliminating srlz.i, not scheduling AR/CR-reads too early (while there are others still pending), scheduling the backing-store switch as well as possible, splitting the BBB bundle into a MIB/MBB pair. Why is it safe to eliminate the srlz.i? Observe that we used to clear bits ~PSR_PRESERVED_BITS in PSR.L. Since PSR_PRESERVED_BITS==PSR.{UP,MFL,MFH,PK,DT,PP,SP,RT,IC}, we ended up clearing PSR.{BE,AC,I,DFL,DFH,DI,DB,SI,TB}. However, PSR.BE : already is turned off in __kernel_syscall_via_epc() PSR.AC : don't care (kernel normally turns PSR.AC on) PSR.I : already turned off by the time fsys_bubble_down gets invoked PSR.DFL: always 0 (kernel never turns it on) PSR.DFH: don't care --- kernel never touches f32-f127 on its own initiative PSR.DI : always 0 (kernel never turns it on) PSR.SI : always 0 (kernel never turns it on) PSR.DB : don't care --- kernel never enables kernel-level breakpoints PSR.TB : must be 0 already; if it wasn't zero on entry to __kernel_syscall_via_epc, the branch to fsys_bubble_down will trigger a taken branch; the taken-trap-handler then converts the syscall into a break-based system-call. In other words: all the bits we're clearying are either 0 already or are don't cares! Thus, we don't have to write PSR.L at all and we don't have to do a srlz.i either. Good for another ~20 cycle improvement for EPC-based heavy-weight syscalls. Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | [IA64] Annotate __kernel_syscall_via_epc() with McKinley dispatch info.David Mosberger-Tang2005-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Two other very minor changes: use "mov.i" instead of "mov" for reading ar.pfs (for clarity; doesn't affect the code at all). Also, predicate the load of r14 for consistency. Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | [IA64] Reschedule __kernel_syscall_via_epc().David Mosberger-Tang2005-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid some stalls, which is good for about 2 cycles when invoking a light-weight handler. When invoking a heavy-weight handler, this helps by about 7 cycles, with most of the improvement coming from the improved branch-prediction achieved by splitting the BBB bundle into two MIB bundles. Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | [IA64] Reschedule break_fault() for better performance.David Mosberger-Tang2005-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch reorganizes break_fault() to optimistically assume that a system-call is being performed from user-space (which is almost always the case). If it turns out that (a) we're not being called due to a system call or (b) we're being called from within the kernel, we fixup the no-longer-valid assumptions in non_syscall() and .break_fixup(), respectively. With this approach, there are 3 major phases: - Phase 1: Read various control & application registers, in particular the current task pointer from AR.K6. - Phase 2: Do all memory loads (load system-call entry, load current_thread_info()->flags, prefetch kernel register-backing store) and switch to kernel register-stack. - Phase 3: Call ia64_syscall_setup() and invoke syscall-handler. Good for 26-30 cycles of improvement on break-based syscall-path. Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | [IA64] In ia64_leave_syscall(), fix comments and whitespace only.David Mosberger-Tang2005-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | [IA64] Schedule ia64_leave_syscall() to read ar.bsp earlierDavid Mosberger-Tang2005-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reschedule code to read ar.bsp as early as possible. To enable this, don't bother clearing some of the registers when we're returning to kernel stacks. Also, instead of trying to support the pNonSys case (which makes no sense), do a bugcheck instead (with break 0). Finally, remove a clear of r14 which is a left-over from the previous patch. Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | [IA64] In syscall-entry, use st8 instead of stf8 to clear pt_regs.r8David Mosberger-Tang2005-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using stf8 seemed like a clever idea at the time, but stf8 forces the cache-line to be invalidated in the L1D (if it happens to be there already). This patch eliminates a guaranteed L1D cache-miss and, by itself, is good for a 1-2 cycle improvement for heavy-weight syscalls. Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | [IA64] On return from syscall, hint b7 with __kernel_syscall_via_epc().David Mosberger-Tang2005-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Why is this a good idea? Clearing b7 to 0 is guaranteed to do us no good and writing it with __kernel_syscall_via_epc() yields a 6 cycle improvement _if_ the application performs another EPC-based system- call without overwriting b7, which is not all that uncommon. Well worth the minimal cost of 1 bundle of code. Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | [IA64] Schedule fp-clearing insns at least 6 cycles after reading ar.bsp.David Mosberger-Tang2005-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Decreases syscall overhead by approximately 6 cycles. Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | [IA64] Use dynamic prediction for RSE-clearing branches.David Mosberger-Tang2005-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This by itself is good for a 1-2 cycle speed up. Effect is bigger when combined with the later patches. Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | [IA64] __ia64_syscall() is no longer used anywhere in the kernel. Remove it.David Mosberger-Tang2005-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | | | | | Merge master.kernel.org:/home/rmk/linux-2.6-serialLinus Torvalds2005-06-30
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| * | | | | | [PATCH] Serial: Split 8250 port table (part 2)Russell King2005-06-29
| | |_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove legacy ISA serial ports for Accent, Boca, Fourport, Hub6 and MCA from the architecture specific serial.h include. The only ports which remain in asm-*/serial.h are the platform specific entries. These should really be converted by platform maintainers to use a platform device, such as can be found in arch/arm/mach-footbridge/isa.c Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | | | [PATCH] ARM: Don't force SIGFPERussell King2005-06-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We were forcing SIGFPE on to a user program for no good reason. Use send_sig_info() instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | | | [PATCH] ARM: Fix VFP to use do_div()Russell King2005-06-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | VFP used __divdi3 64-bit division needlessly. Convert it to use our 64-bit by 32-bit division instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | | | [PATCH] ARM: 2771/1: Dynamic Tick support for OMAP, take 4Tony Lindgren2005-06-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Tony Lindgren This patch adds support for Dynamic Tick Timer for OMAP. This patch is an updated version of ARM patch 2642/1 to make it work with the already integrated generic ARM dyntick support. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | | | [PATCH] ARM: Remove nmi_tick from integrator platformsRussell King2005-06-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The nmi watchdog code hasn't been merged for this platform yet. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | | | [PATCH] ARM: 2723/2: remove __udivdi3 and __umoddi3 from the kernelNicolas Pitre2005-06-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Nicolas Pitre Those are big, slow and generally not recommended for kernel code. They are even not present on i386. So it should be concluded that one could as well get away with do_div() alone. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | | | [PATCH] ARM: 2769/1: cpu_init() stack setup fixCatalin Marinas2005-06-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Catalin Marinas The compiler allocates r14 for the stk variable in the __asm__ directive. This is a shadowed register and gets changed when the mode is changed, causing random values in the SP register. The patch adds a clobber for the r14 register. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | | | [PATCH] ARM: Convert ARM timer implementations to use readl/writelRussell King2005-06-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert ARMs timer implementations to use readl/writel instead of accessing the registers via a struct. People have recently asked if accessing timers via a structure is the "right way" and its not the Linux way. So fix this code to conform to "The Linux Way"(tm). Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
* | | | | | [PATCH] ARM: 2765/1: S3C24XX - small cleanups in arch/arm/mach-s3c2410Ben Dooks2005-06-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Ben Dooks Re-tab the devs.c file, and change the initialiser for the mach-vr1000.c to use `.xxx = yyy` form. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | | | [PATCH] ARM: 2764/1: S3C24XX - Common PM functions for Simtec boardsBen Dooks2005-06-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Ben Dooks All current S3C24XX implementations from Simtec share the same requirements for suspend/resume information. This patch moves the save code out of the mach-bast.c file, and into it's own so it can be shared by all the current Simtec S3C24XX implementations. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | | | Merge with ../linux-2.6-smpRussell King2005-06-29
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| * | | | | [PATCH] ARM SMP: Add IPI support code for SMP TLB flushingRussell King2005-06-28
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | | [PATCH] ARM SMP: Use local_flush_tlb* where we really want to be localRussell King2005-06-28
| |/ / / / | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | | [PATCH] sparc32: Kconfig fixupsWilliam Lee Irwin III2005-06-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Something reverted most of the arch/sparc/Kconfig changes, leaving arch/sparc/ unconfigurable. This patch re-removes the parts made redundant by drivers/Kconfig in addition to a mysterious, spurious second instance of source "mm/Kconfig". cvs strikes again? Signed-off-by: William Irwin <wli@holomorphy.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | | | | [PATCH] irqpollAlan Cox2005-06-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Anyone reporting a stuck IRQ should try these options. Its effectiveness varies we've found in the Fedora case. Quite a few systems with misdescribed IRQ routing just work when you use irqpoll. It also fixes up the VIA systems although thats now fixed with the VIA quirk (which we could just make default as its what Redmond OS does but Linus didn't like it historically). A small number of systems have jammed IRQ sources or misdescribes that cause an IRQ that we have no handler registered anywhere for. In those cases it doesn't help. Signed-off-by: Alan Cox <number6@the-village.bc.nu> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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