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* x86, perf: P4 PMU -- check for proper event index in RAW eventsCyrill Gorcunov2010-05-08
| | | | | | | | | | | | RAW events are special and we should be ready for user passing in insane event index values. Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Lin Ming <ming.m.lin@intel.com> LKML-Reference: <20100508112717.315897547@openvz.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86, perf: P4 PMU -- Get rid of redundant check for array indexCyrill Gorcunov2010-05-08
| | | | | | | | | | | | The caller already has done such a check. And it was wrong anyway, it had to be '>=' rather than '>' Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Lin Ming <ming.m.lin@intel.com> LKML-Reference: <20100508112717.130386882@openvz.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86, perf: P4 PMU -- protect sensible procedures from preemptionCyrill Gorcunov2010-05-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Steven reported: | | I'm getting: | | Pid: 3477, comm: perf Not tainted 2.6.34-rc6 #2727 | Call Trace: | [<ffffffff811c7565>] debug_smp_processor_id+0xd5/0xf0 | [<ffffffff81019874>] p4_hw_config+0x2b/0x15c | [<ffffffff8107acbc>] ? trace_hardirqs_on_caller+0x12b/0x14f | [<ffffffff81019143>] hw_perf_event_init+0x468/0x7be | [<ffffffff810782fd>] ? debug_mutex_init+0x31/0x3c | [<ffffffff810c68b2>] T.850+0x273/0x42e | [<ffffffff810c6cab>] sys_perf_event_open+0x23e/0x3f1 | [<ffffffff81009e6a>] ? sysret_check+0x2e/0x69 | [<ffffffff81009e32>] system_call_fastpath+0x16/0x1b | | When running perf record in latest tip/perf/core | Due to the fact that p4 counters are shared between HT threads we synthetically divide the whole set of counters into two non-intersected subsets. And while we're "borrowing" counters from these subsets we should not be preempted (well, strictly speaking in p4_hw_config we just pre-set reference to the subset which allow to save some cycles in schedule routine if it happens on the same cpu). So use get_cpu/put_cpu pair. Also p4_pmu_schedule_events should use smp_processor_id rather than raw_ version. This allow us to catch up preemption issue (if there will ever be). Reported-by: Steven Rostedt <rostedt@goodmis.org> Tested-by: Steven Rostedt <rostedt@goodmis.org> Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Lin Ming <ming.m.lin@intel.com> LKML-Reference: <20100508112716.963478928@openvz.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86, perf: P4 PMU -- configure predefined eventsCyrill Gorcunov2010-05-08
| | | | | | | | | | | | If an event is not RAW we should not exit p4_hw_config early but call x86_setup_perfctr as well. Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Lin Ming <ming.m.lin@intel.com> Cc: Robert Richter <robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* perf, x86: implement group scheduling transactional APIsLin Ming2010-05-07
| | | | | | | | | | | | | Convert to the transactional PMU API and remove the duplication of group_sched_in(). Reviewed-by: Stephane Eranian <eranian@google.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: David Miller <davem@davemloft.net> Cc: Paul Mackerras <paulus@samba.org> LKML-Reference: <1272002172.5707.61.camel@minggr.sh.intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* perf, x86: Improve the PEBS ABIPeter Zijlstra2010-05-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | Rename perf_event_attr::precise to perf_event_attr::precise_ip and widen it to 2 bits. This new field describes the required precision of the PERF_SAMPLE_IP field: 0 - SAMPLE_IP can have arbitrary skid 1 - SAMPLE_IP must have constant skid 2 - SAMPLE_IP requested to have 0 skid 3 - SAMPLE_IP must have 0 skid And modify the Intel PEBS code accordingly. The PEBS implementation now supports up to precise_ip == 2, where we perform the IP fixup. Also s/PERF_RECORD_MISC_EXACT/&_IP/ to clarify its meaning, this bit should be set for each PERF_SAMPLE_IP field known to match the actual instruction triggering the event. This new scheme allows for a PEBS mode that uses the buffer for more than a single event. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Stephane Eranian <eranian@google.com> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* perf, x86: Consolidate some code repetitionPeter Zijlstra2010-05-07
| | | | | | | | Remove some duplicated logic. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* perf, x86: Remove PEBS SAMPLE_RAW supportPeter Zijlstra2010-05-07
| | | | | | | | Its broken, we really should get PERF_SAMPLE_REGS sorted. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* perf, x86: Use weight instead of cmask in for_each_event_constraint()Robert Richter2010-05-07
| | | | | | | | | | | | | | | | There may exist constraints with a cmask set to zero. In this case for_each_event_constraint() will not work properly. Now weight is used instead of the cmask for loop exit detection. Weight is always a value other than zero since the default contains the HWEIGHT from the counter mask and in other cases a value of zero does not fit too. This is in preparation of ibs event constraints that wont have a cmask. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <1271190201-25705-7-git-send-email-robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* perf, x86: Pass enable bit mask to __x86_pmu_enable_event()Robert Richter2010-05-07
| | | | | | | | | | | | To reuse this function for events with different enable bit masks, this mask is part of the function's argument list now. The function will be used later to control ibs events too. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <1271190201-25705-6-git-send-email-robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* perf, x86: Call x86_setup_perfctr() from .hw_config()Robert Richter2010-05-07
| | | | | | | | | | | | | The perfctr setup calls are in the corresponding .hw_config() functions now. This makes it possible to introduce config functions for other pmu events that are not perfctr specific. Also, all of a sudden the code looks much nicer. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <1271190201-25705-4-git-send-email-robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* perf, x86: Move x86_setup_perfctr()Robert Richter2010-05-07
| | | | | | | | | Move x86_setup_perfctr(), no other changes made. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <1271190201-25705-3-git-send-email-robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* perf, x86: Move perfctr init code to x86_setup_perfctr()Robert Richter2010-05-07
| | | | | | | | | | | | | Split __hw_perf_event_init() to configure pmu events other than perfctrs. Perfctr code is moved to a separate function x86_setup_perfctr(). This and the following patches refactor the code. Split in multiple patches for better review. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <1271190201-25705-2-git-send-email-robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* Merge branch 'perf/urgent' into perf/coreIngo Molnar2010-05-07
|\ | | | | | | | | | | Merge reason: Resolve patch dependency Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * Merge branch 'x86-fixes-for-linus' of ↵Linus Torvalds2010-05-04
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux-2.6-tip * 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux-2.6-tip: powernow-k8: Fix frequency reporting x86: Fix parse_reservetop() build failure on certain configs x86: Fix NULL pointer access in irq_force_complete_move() for Xen guests x86: Fix 'reservetop=' functionality
| | * powernow-k8: Fix frequency reportingMark Langsdorf2010-05-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With F10, model 10, all valid frequencies are in the ACPI _PST table. Cc: <stable@kernel.org> # 33.x 32.x Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com> LKML-Reference: <1270065406-1814-6-git-send-email-bp@amd64.org> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> Reviewed-by: Thomas Renninger <trenn@suse.de> Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| | * x86: Fix parse_reservetop() build failure on certain configsIngo Molnar2010-05-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e67a807 ("x86: Fix 'reservetop=' functionality") added a fixup_early_ioremap() call to parse_reservetop() and declared it in io.h. But asm/io.h was only included indirectly - and on some configs not at all, causing a build failure on those configs. Cc: Liang Li <liang.li@windriver.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Cc: Wang Chen <wangchen@cn.fujitsu.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Andrew Morton <akpm@linux-foundation.org> LKML-Reference: <1272621711-8683-1-git-send-email-liang.li@windriver.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| | * x86: Fix NULL pointer access in irq_force_complete_move() for Xen guestsPrarit Bhargava2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upstream PV guests fail to boot because of a NULL pointer in irq_force_complete_move(). It is possible that xen guests have irq_desc->chip_data = NULL. Test for NULL chip_data pointer before attempting to complete an irq move. Signed-off-by: Prarit Bhargava <prarit@redhat.com> LKML-Reference: <20100427152434.16193.49104.sendpatchset@prarit.bos.redhat.com> Acked-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com> Cc: <stable@kernel.org> [2.6.33]
| | * x86: Fix 'reservetop=' functionalityLiang Li2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When specifying the 'reservetop=0xbadc0de' kernel parameter, the kernel will stop booting due to a early_ioremap bug that relates to commit 8827247ff. The root cause of boot failure problem is the value of 'slot_virt[i]' was initialized in setup_arch->early_ioremap_init(). But later in setup_arch, the function 'parse_early_param' will modify 'FIXADDR_TOP' when 'reservetop=0xbadc0de' being specified. The simplest fix might be use __fix_to_virt(idx0) to get updated value of 'FIXADDR_TOP' in '__early_ioremap' instead of reference old value from slot_virt[slot] directly. Changelog since v0: -v1: When reservetop being handled then FIXADDR_TOP get adjusted, Hence check prev_map then re-initialize slot_virt and PMD based on new FIXADDR_TOP. -v2: place fixup_early_ioremap hence call early_ioremap_init in reserve_top_address to re-initialize slot_virt and corresponding PMD when parse_reservertop -v3: move fixup_early_ioremap out of reserve_top_address to make sure other clients of reserve_top_address like xen/lguest won't broken Signed-off-by: Liang Li <liang.li@windriver.com> Tested-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Acked-by: Yinghai Lu <yinghai@kernel.org> Acked-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Cc: Wang Chen <wangchen@cn.fujitsu.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Andrew Morton <akpm@linux-foundation.org> LKML-Reference: <1272621711-8683-1-git-send-email-liang.li@windriver.com> [ fixed three small cleanliness details in fixup_early_ioremap() ] Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | Fix the x86_64 implementation of call_rwsem_wait()David Howells2010-05-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | The x86_64 call_rwsem_wait() treats the active state counter part of the R/W semaphore state as being 16-bit when it's actually 32-bit (it's half of the 64-bit state). It should do "decl %edx" not "decw %dx". Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| * | Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2010-04-30
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (27 commits) MIPS: Loongson 2F: Fix of problems introduced by -mfix-loongson2f-jump MIPS: Loongson-2F: Use CONFIG_CPU_JUMP_WORKAROUNDS to control workarounds. MIPS: Loongson 2F: Enable fixups of the latest binutils MIPS: Loongson: Add CPU_LOONGSON2F_WORKAROUNDS MIPS: Kconfig: Make Broadcom SoC support naming consistent MIPS: BCM63xx: Update defconfig MIPS: oprofile: Fix breakage when CONFIG_OPROFILE=m STAGING: octeon-ethernet: Use proper phy addresses for Movidis hardware. NET: mdio-octeon: Enable the hardware before using it. I2C: Fix section mismatch errors in i2c-octeon.c MIPS: Loongson: Fix LOONGSON_ADDRWIN_CFG macro. MIPS: Loongson: Fix phys_mem_access_prot() check MIPS: Loongson: Fix find_vga_mem_init() MIPS: Loongson: Fix typo in gdium mach type string. MIPS: Use CKSEG1ADDR for uncached handler MIPS: Check for accesses beyond the end of the PGD. MIPS: Use uasm_i_ds{r,l}l_safe() instead of uasm_i_ds{r,l}l() in tlbex.c MIPS: Add uasm_i_dsrl_safe() and uasm_i_dsll_safe() to uasm. MIPS: die() does not call die notifier chain MIPS: Swarm, Littlesur: Enable PATA platform driver. ...
| | * | MIPS: Loongson 2F: Fix of problems introduced by -mfix-loongson2f-jumpWu Zhangjin2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The -mfix-loongson2f-jump option provided by latest CVS binutils have fixed the out-of-order issue of Loongson-2F described in chapter 15 of the Loongson2F User Manual [1, 2], but introduced some problems. The option changes all of the jump target to "addr & 0xcfffffff" through the at($1) register, but for the reboot address of Loongson 2F 0xbfc00000 this is wrong. Avoids the problem via telling the assembler to not use the $at register. [1] Loongson2F User Manual (Chinese Version) http://www.loongson.cn/uploadfile/file/200808211 [2] English Version of Chapter 15: http://groups.google.com.hk/group/loongson-dev/msg/e0d2e220958f10a6?dmode=source Reported-and-tested-by: Liu Shiwei <liushiwei@gmail.com> Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1109/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Loongson-2F: Use CONFIG_CPU_JUMP_WORKAROUNDS to control workarounds.Wu Zhangjin2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1106/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Loongson 2F: Enable fixups of the latest binutilsWu Zhangjin2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the "Fixups of Loongson2F" patch [1] having been applied to binutils for binutils 2.20.1 we now can use it's time to enable the options provided by the patch to compile the kernel. Without these fixups, the system may hang if the erratum is triggered. For more information on these fixups please refer to the following references. [1] "Fixups of Loongson2F" patch for binutils(actually for gas) http://sourceware.org/ml/binutils/2009-11/msg00387.html [2] Chapter 15 of "Loongson2F User Manual"(Chinese Version) http://www.loongson.cn/uploadfile/file/200808211 [3] Chapter 15 of the English version Loongson 2F User Manual http://groups.google.com.hk/group/loongson-dev/msg/e0d2e220958f10a6?dmode=source Signed-off-by: Zhang Le <r0bertz@gentoo.org> Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: Zhang Le <r0bertz@gentoo.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1106/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Loongson: Add CPU_LOONGSON2F_WORKAROUNDSWu Zhangjin2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As documented in the Loongson 2F User Manual [2, 3], the old Loongson2F series (2F01 / 2F02) have the NOP & JUMP issues which requires workarounds in the kernel and binutils. This issue has been rectified in Loongson 2F series 2F03 so no workarounds needed. Now that the workarounds [1] adding the the -mfix-loongson2f-nop and -mfix-loongson2f-jump options have been comitted to the binutils the CVS repository), we can add the workarounds in the kernel. The workarounds have no significant side effect on the system but may decrease performance so we control them through a a new CPU_LOONGSON2F_WORKAROUNDS config option allowing the users to only enable it as necessary. [1] "Fixups of Loongson2F" patch for binutils(actually for gas) http://sourceware.org/ml/binutils/2009-11/msg00387.html [2] Chapter 15 of "Loongson2F User Manual"(Chinese Version) http://www.loongson.cn/uploadfile/file/200808211 [3] English Version of the above chapter 15 http://groups.google.com.hk/group/loongson-dev/msg/e0d2e220958f10a6?dmode=source Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1105/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Kconfig: Make Broadcom SoC support naming consistentFlorian Fainelli2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Florian Fainelli <ffainelli@freebox.fr> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1082/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: BCM63xx: Update defconfigFlorian Fainelli2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the defconfig was out-of-sync since 2.6.30-rc6, update it with the new symbols and enable BCM6338, 6345, wireless, b43 driver and LEDs support. Signed-off-by: Fainelli <ffainelli@freebox.fr> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1081/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: oprofile: Fix breakage when CONFIG_OPROFILE=mWu Zhangjin2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the oprofile is compiled as a module do_IRQ() is not called in arch/mips/loongson/lemote-2f/irq.c due to a wrong #ifdef there. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1143/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Loongson: Fix LOONGSON_ADDRWIN_CFG macro.Arnaud Patard2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's a typo in the LOONGSON_ADDRWIN_CFG macro. The cpu window mmap register address should contain the destination parameters not the source one. This has not been noticed because the code is only using source = destination. Signed-off-by: Arnaud Patard <apatard@mandriva.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1162/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Loongson: Fix phys_mem_access_prot() checkArnaud Patard2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The check used to determine if uncached accelerated should be used or not is wrong. The parenthesis are misplaced and making the test fail. Signed-off-by: Arnaud Patard <apatard@mandriva.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1161/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Loongson: Fix find_vga_mem_init()Richard LIU2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows to use all display device for instance DISPLAY_OTHER like SM501. Signed-off-by: Arnaud Patard <apatard@mandriva.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1160/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Loongson: Fix typo in gdium mach type string.Arnaud Patard2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's not "gidum" but "gdium". Signed-off-by: Arnaud Patard <apatard@mandriva.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1159/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Use CKSEG1ADDR for uncached handlerSebastian Andrzej Siewior2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "MIPS: Calculate proper ebase value for 64-bit kernels" 9af43ea080dd5d6c7b34f38261780e5dd43537bc (lmo) rsp. f6be75d03c8870be91e6e2a195648ece04b6bb16 (kernel.org) broke some 64-bit MIPS systems. Before this we were using XKPHYS/cached as ebase and computed the uncached xphsys/unchached address for that area. After that commit ebase became a 32-bit compat address and convert does not work anymore. We now should use CKSEG1 for this. CKSEG1ADDR does just that in 32-bit and 64-bit. Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc> To: Ralf Baechle <ralf@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1149/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Check for accesses beyond the end of the PGD.David Daney2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some combinations of PAGE_SIZE and vmbits, it is possible to have userspace access that are beyond what is covered by the PGD, but within vmbits. Such an access would cause the TLB refill handler to load garbage values for PMD and PTE potentially giving userspace access to parts of the physical address space to which it is not entitled. In the TLB refill hot path, we add a single dsrl instruction so we can check if any bits outside of the range covered by the PGD are set. In the vmalloc side we then separate the bad case from the normal vmalloc case and call tlb_do_page_fault_0 if warranted. This slows us down a bit, but has the benefit of yielding deterministic behavior. [Ralf: Fixed build error for 32-bit kernels.] [Ralf: Folded lmo commit c8c0e22b2aa3982852b44279638ef37f9aa31b7d into this commit.] Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1152/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
| | * | MIPS: Use uasm_i_ds{r,l}l_safe() instead of uasm_i_ds{r,l}l() in tlbex.cDavid Daney2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes the code somewhat cleaner while reducing the risk of shift amount overflows when various page table related options are changed. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1154/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Add uasm_i_dsrl_safe() and uasm_i_dsll_safe() to uasm.David Daney2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows us to clean up the code by not having to explicitly code checks for shift amounts greater than 32. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1153/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: die() does not call die notifier chainYury Polyanskiy2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MIPS implementation of die() forgets to call notify_die() and thus notifiers registered via register_die_notifier() are not called. This results in kgdb not being activated on exceptions. The only subtlety is that notify_die declares its regs argument w/o const, so the const had to be removed from mips die() as well. [Ralf: Fixed build error for SGI IP22 and IP28 platforms.] Signed-off-by: Yury Polyanskiy <ypolyans@princeton.edu> Cc: linux-mips@linux-mips.org Patchworks: http://patchwork.linux-mips.org/patch/1142/ Acked-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
| | * | MIPS: Swarm, Littlesur: Enable PATA platform driver.Sebastian Andrzej Siewior2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to include/asm/sibyte/swarm.h both systems provide a platform device for the ide controler. Until now the IDE subsystem was used which is deprecated by now. The same structure can be used with the PATA driver. Signed-off-by: Sebastian Andrzej Siewior <sebatian@breakpoint.cc> Cc: tbm@cyrius.com Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1127/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: DB1200: PCMCIA card detection must not be auto-enabled.Manuel Lauss2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Same issues as SD card detection: One of both is always triggering and the handlers take care to shut it up and enable the other. To avoid messages about "unbalanced interrupt enable/disable" they must not be automatically enabled when initally requested. This was not an issue with the db1200_defconfig due to fortunate timings; on a build without network chip support the warnings appear. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1133/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: SB1250: Include correct header and fix a warningSebastian Andrzej Siewior2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arch/mips/pci/pci-sb1250.c: In function sb1250_pcibios_init: | arch/mips/pci/pci-sb1250.c:257: warning: assignment makes integer from pointer without a cast | arch/mips/pci/pci-sb1250.c:285: error: MAX_NR_CONSOLES undeclared (first use in this function) | arch/mips/pci/pci-sb1250.c:285: error: (Each undeclared identifier is reported only once | arch/mips/pci/pci-sb1250.c:285: error: for each function it appears in.) Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1136/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Fixup screen_info struct initializationsSebastian Andrzej Siewior2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |arch/mips/sibyte/swarm/setup.c:153: | warning: large integer implicitly truncated to unsigned type The field was changed in d9b26352 aka ("x86, setup: Store the boot cursor state"). This patch changes the values back they way they were before this extra field got introduced. While here, the other two boards are also converted to C99 initializer. Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1137/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: cmpxchg.h: Fix excessive indentation.Ralf Baechle2010-04-30
| | | | | | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Don't vmap things at address zero.David Daney2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the 64-bit kernel we use swapper_pg_dir for three different things. 1) xuseg mappings for kernel threads. 2) vmap mappings for all kernel-space accesses in xkseg. 3) vmap mappings for kernel modules in ksseg (kseg2). Due to how the TLB refill handlers work, any mapping established in xkseg or ksseg will also establish a xuseg mapping that should never be used by the kernel. In order to be able to use exceptions to trap NULL pointer dereferences, we need to ensure that nothing is mapped at address zero. Since vmap mappings in xkseg are reflected in xuseg, this means we need to ensure that there are no vmap mappings established at the start of xkseg. So we move back VMALLOC_START to avoid establishing vmap mappings at the start of xkseg. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1129/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: PNX8550: Fix build error, broken by:Ralf Baechle2010-04-30
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 5a0e3ad6af8660be21ca98a971cd00f331318c05 Author: Tejun Heo <tj@kernel.org> Date: Wed Mar 24 17:04:11 2010 +0900 include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h Since a while the few headers included don't drag in <linux/kernel.h> anymore, thus no more prototype of printk() resulting in: CC arch/mips/nxp/pnx8550/common/reset.o /home/ralf/src/linux/upstream-linus/arch/mips/nxp/pnx8550/common/reset.c: In function 'pnx8550_machine_restart': /home/ralf/src/linux/upstream-linus/arch/mips/nxp/pnx8550/common/reset.c:31: error: implicit declaration of function 'printk' /home/ralf/src/linux/upstream-linus/arch/mips/nxp/pnx8550/common/reset.c:33: error: 'NULL' undeclared (first use in this function) /home/ralf/src/linux/upstream-linus/arch/mips/nxp/pnx8550/common/reset.c:33: error: (Each undeclared identifier is reported only once /home/ralf/src/linux/upstream-linus/arch/mips/nxp/pnx8550/common/reset.c:33: error: for each function it appears in.) make[3]: *** [arch/mips/nxp/pnx8550/common/reset.o] Error 1 Fixed by including <linux/kernel.h> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * / musb: fix power field to hold all possible valuesAjay Kumar Gupta2010-04-30
| |/ | | | | | | | | | | | | | | | | | | MUSB can supply upto 500mA such as, AM3517 and OMAP3EVM Rev >=E and thus the 'power' field has to hold values above 255. Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@nokia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* | hw-breakpoints: Get the number of available registers on boot dynamicallyFrederic Weisbecker2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The breakpoint generic layer assumes that archs always know in advance the static number of address registers available to host breakpoints through the HBP_NUM macro. However this is not true for every archs. For example Arm needs to get this information dynamically to handle the compatiblity between different versions. To solve this, this patch proposes to drop the static HBP_NUM macro and let the arch provide the number of available slots through a new hw_breakpoint_slots() function. For archs that have CONFIG_HAVE_MIXED_BREAKPOINTS_REGS selected, it will be called once as the number of registers fits for instruction and data breakpoints together. For the others it will be called first to get the number of instruction breakpoint registers and another time to get the data breakpoint registers, the targeted type is given as a parameter of hw_breakpoint_slots(). Reported-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com> Acked-by: Paul Mundt <lethal@linux-sh.org> Cc: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Cc: K. Prasad <prasad@linux.vnet.ibm.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Jason Wessel <jason.wessel@windriver.com> Cc: Ingo Molnar <mingo@elte.hu>
* | hw-breakpoints: Separate constraint space for data and instruction breakpointsFrederic Weisbecker2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two outstanding fashions for archs to implement hardware breakpoints. The first is to separate breakpoint address pattern definition space between data and instruction breakpoints. We then have typically distinct instruction address breakpoint registers and data address breakpoint registers, delivered with separate control registers for data and instruction breakpoints as well. This is the case of PowerPc and ARM for example. The second consists in having merged breakpoint address space definition between data and instruction breakpoint. Address registers can host either instruction or data address and the access mode for the breakpoint is defined in a control register. This is the case of x86 and Super H. This patch adds a new CONFIG_HAVE_MIXED_BREAKPOINTS_REGS config that archs can select if they belong to the second case. Those will have their slot allocation merged for instructions and data breakpoints. The others will have a separate slot tracking between data and instruction breakpoints. Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com> Acked-by: Paul Mundt <lethal@linux-sh.org> Cc: Will Deacon <will.deacon@arm.com> Cc: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Cc: K. Prasad <prasad@linux.vnet.ibm.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu>
* | hw-breakpoints: Change/Enforce some breakpoints policiesFrederic Weisbecker2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current policies of breakpoints in x86 and SH are the following: - task bound breakpoints can only break on userspace addresses - cpu wide breakpoints can only break on kernel addresses The former rule prevents ptrace breakpoints to be set to trigger on kernel addresses, which is good. But as a side effect, we can't breakpoint on kernel addresses for task bound breakpoints. The latter rule simply makes no sense, there is no reason why we can't set breakpoints on userspace while performing cpu bound profiles. We want the following new policies: - task bound breakpoint can set userspace address breakpoints, with no particular privilege required. - task bound breakpoints can set kernelspace address breakpoints but must be privileged to do that. - cpu bound breakpoints can do what they want as they are privileged already. To implement these new policies, this patch checks if we are dealing with a kernel address breakpoint, if so and if the exclude_kernel parameter is set, we tell the user that the breakpoint is invalid, which makes a good generic ptrace protection. If we don't have exclude_kernel, ensure the user has the right privileges as kernel breakpoints are quite sensitive (risk of trap recursion attacks and global performance impacts). [ Paul Mundt: keep addr space check for sh signal delivery and fix double function declaration] Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Cc: K. Prasad <prasad@linux.vnet.ibm.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Jason Wessel <jason.wessel@windriver.com> Cc: Ingo Molnar <mingo@elte.hu> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | hw-breakpoints: Tag ptrace breakpoint as exclude_kernelFrederic Weisbecker2010-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tag ptrace breakpoints with the exclude_kernel attribute set. This will make it easier to set generic policies on breakpoints, when it comes to ensure nobody unpriviliged try to breakpoint on the kernel. Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com> Acked-by: Paul Mundt <lethal@linux-sh.org> Cc: Will Deacon <will.deacon@arm.com> Cc: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Cc: K. Prasad <prasad@linux.vnet.ibm.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu>
* | Merge commit 'v2.6.34-rc6' into perf/coreIngo Molnar2010-04-30
|\| | | | | | | | | | | Merge reason: update to the latest -rc. Signed-off-by: Ingo Molnar <mingo@elte.hu>
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