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* [SPARC64]: Fix hypervisor call arg passing.David S. Miller2006-03-20
| | | | | | Function goes in %o5, args go in %o0 --> %o5. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Implement SUN4V PCI config space access.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: More SUN4V PCI controller work.David S. Miller2006-03-20
| | | | | | | | | | Add assembler file for PCI hypervisor calls. Setup basic skeleton of SUN4V PCI controller driver. Add 32-bit devhandle to PBM struct, as this is needed for hypervisor calls. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Beginnings of SUN4V PCI controller support.David S. Miller2006-03-20
| | | | | | | | Abstract out IOMMU operations so that we can have a different set of calls on sun4v, which needs to do things through hypervisor calls. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fetch cpu mid properly on sun4v.David S. Miller2006-03-20
| | | | | | | If there is a "cpuid" property, use that. Else suck it out of the top bits of the "reg" property. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: SUN4V memory exception trap handlers.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Hypervisor TSB context switching.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Implement sun4v TSB miss handlers.David S. Miller2006-03-20
| | | | | | | | | | | When we register a TSB with the hypervisor, so that it or hardware can handle TLB misses and do the TSB walk for us, the hypervisor traps down to these trap when it incurs a TSB miss. Processing is simple, we load the missing virtual address and context, and do a full page table walk. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: kernel/cpu.c needs asm/spitfire.hDavid S. Miller2006-03-20
| | | | | | For 'tlb_type'. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Print ARCH as SUN4V when tlb_type is hypervisor.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Detect sun4v early in boot process.David S. Miller2006-03-20
| | | | | | | | | | | | | We look for "SUNW,sun4v" in the 'compatible' property of the root OBP device tree node. Protect every %ver register access, to make sure it is not touched on sun4v, as %ver is hyperprivileged there. Lock kernel TLB entries using hypervisor calls instead of calls into OBP. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Sun4v cross-call sending support.David S. Miller2006-03-20
| | | | | | | | | | | Technically the hypervisor call supports sending in a list of all cpus to get the cross-call, but I only pass in one cpu at a time for now. The multi-cpu support is there, just ifdef'd out so it's easy to enable or delete it later. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Sun4v interrupt handling.David S. Miller2006-03-20
| | | | | | | | | | | | | | | | | Sun4v has 4 interrupt queues: cpu, device, resumable errors, and non-resumable errors. A set of head/tail offset pointers help maintain a work queue in physical memory. The entries are 64-bytes in size. Each queue is allocated then registered with the hypervisor as we bring cpus up. The two error queues each get a kernel side buffer that we use to quickly empty the main interrupt queue before we call up to C code to log the event and possibly take evasive action. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Allocate and register the 4 sun4v mondo queues at bootup.David S. Miller2006-03-20
| | | | | | Needs to occur before we enable PSTATE_IE in %pstate. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Verify all trap_per_cpu assembler offsets in trap_init()David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Patch up mmu context register writes for sun4v.David S. Miller2006-03-20
| | | | | | sun4v uses ASI_MMU instead of ASI_DMMU Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Register per-cpu fault status area with sun4v hypervisor.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Niagara copy/clear page.David S. Miller2006-03-20
| | | | | | | | | | Happily we have no D-cache aliasing issues on these chips, so the implementation is very straightforward. Add a stub in bootup which will be where the patching calls will be made for niagara/sun4v/hypervisor. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Rename gl_{1,2}insn_patch --> sun4v_{1,2}insn_patchDavid S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Initial sun4v TLB miss handling infrastructure.David S. Miller2006-03-20
| | | | | | | | | | Things are a little tricky because, unlike sun4u, we have to: 1) do a hypervisor trap to do the TLB load. 2) do the TSB lookup calculations by hand Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add missing memory barriers to instruction patching functions.David S. Miller2006-03-20
| | | | | | V9 requires a write memory barrier before the instruction flush. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Sanitize %pstate writes for sun4v.David S. Miller2006-03-20
| | | | | | | | If we're just switching between different alternate global sets, nop it out on sun4v. Also, get rid of all of the alternate global save/restore in the OBP CIF trampoline code. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill all %pstate changes in context switch code.David S. Miller2006-03-20
| | | | | | | | | | | | | | | They are totally unnecessary because: 1) Interrupts are already disabled when switch_to() runs. 2) We don't use hard-coded alternate globals any longer. This found a case in rtrap, which still assumed alternate global %g6 was current_thread_info(), and that is fixed by this changeset as well. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add initial code to twiddle %gl on trap entry/exit.David S. Miller2006-03-20
| | | | | | | Instead of setting/clearing PSTATE_AG we have to change the %gl register value on sun4v. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fill dead cycles on trap entry with real work.David S. Miller2006-03-20
| | | | | | | | | As we save trap state onto the stack, the store buffer fills up mid-way through and we stall for several cycles as the store buffer trickles out to the L2 cache. Meanwhile we can do some privileged register reads and other calculations, essentially for free. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add sun4v case to __GET_CPUID() patch tables.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Niagara optimized memcpy() and copy_{to,from}_user().David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add some hypervisor tlb_type checks.David S. Miller2006-03-20
| | | | | | | And more consistently check cheetah{,_plus} instead of assuming anything not spitfire is cheetah{,_plus}. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: SUN4V hypervisor TLB flush support code.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Refine register window trap handling.David S. Miller2006-03-20
| | | | | | | | | | | When saving and restoing trap state, do the window spill/fill handling inline so that we never trap deeper than 2 trap levels. This is important for chips like Niagara. The window fixup code is massively simplified, and many more improvements are now possible. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add explicit register args to trap state loading macros.David S. Miller2006-03-20
| | | | | | | This, as well as making the code cleaner, allows a simplification in the TSB miss handling path. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Refine code sequences to get the cpu id.David S. Miller2006-03-20
| | | | | | | | | | | | | | | | | | On uniprocessor, it's always zero for optimize that. On SMP, the jmpl to the stub kills the return address stack in the cpu branch prediction logic, so expand the code sequence inline and use a code patching section to fix things up. This also always better and explicit register selection, which will be taken advantage of in a future changeset. The hard_smp_processor_id() function is big, so do not inline it. Fix up tests for Jalapeno to also test for Serrano chips too. These tests want "jbus Ultra-IIIi" cases to match, so that is what we should test for. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Turn off TSB growing for now.David S. Miller2006-03-20
| | | | | | | | | | | | | | | | | | | | | | | | There are several tricky races involved with growing the TSB. So just use base-size TSBs for user contexts and we can revisit enabling this later. One part of the SMP problems is that tsb_context_switch() can see partially updated TSB configuration state if tsb_grow() is running in parallel. That's easily solved with a seqlock taken as a writer by tsb_grow() and taken as a reader to capture all the TSB config state in tsb_context_switch(). Then there is flush_tsb_user() running in parallel with a tsb_grow(). In theory we could take the seqlock as a reader there too, and just resample the TSB pointer and reflush but that looks really ugly. Lastly, I believe there is a case with threads that results in a TSB entry lock bit being set spuriously which will cause the next access to that TSB entry to wedge the cpu (since the TSB entry lock bit will never clear). It's either copy_tsb() or some bug elsewhere in the TSB assembly. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Correctable ECC errors cannot occur at trap level > 0.David S. Miller2006-03-20
| | | | | | | | | | | | | The are distrupting, which by the sparc v9 definition means they can only occur when interrupts are enabled in the %pstate register. This never occurs in any of the trap handling code running at trap levels > 0. So just mark it as an unexpected trap. This allows us to kill off the cee_stuff member of struct thread_info. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Access TSB with physical addresses when possible.David S. Miller2006-03-20
| | | | | | | | | | | | | This way we don't need to lock the TSB into the TLB. The trick is that every TSB load/store is registered into a special instruction patch section. The default uses virtual addresses, and the patch instructions use physical address load/stores. We can't do this on all chips because only cheetah+ and later have the physical variant of the atomic quad load. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Don't clobber alt-global %g4 on window fixups.David S. Miller2006-03-20
| | | | | | | | If we are returning back to kernel mode, %g4 could be live (for example, in the case where we window spill in the etrap code). So do not change it's value if going back to kernel. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix race in LOAD_PER_CPU_BASE()David S. Miller2006-03-20
| | | | | | | | | | Since we use %g5 itself as a temporary, it can get clobbered if we take an interrupt mid-stream and thus cause end up with the final %g5 value too early as a result of rtrap processing. Set %g5 at the very end, atomically, to avoid this problem. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill swapper_pgd_zero, totally unused.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix too early reference to %g6David S. Miller2006-03-20
| | | | | | | | | %g6 is not necessarily set to current_thread_info() at sparc64_realfault_common. So store the fault code and address after we invoke etrap and %g6 is properly set up. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill hard-coded %pstate setting in sparc_exit.David S. Miller2006-03-20
| | | | | | | Just flip the bit off of whatever it's currently set to. PSTATE_IE is guarenteed to be enabled when we get here. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Increase swapper_tsb size to 32K.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill sole argument passed to setup_tba().David S. Miller2006-03-20
| | | | | | No longer used, and move extern declaration to a header file. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill PROM locked TLB entry preservation code.David S. Miller2006-03-20
| | | | | | | It is totally unnecessary complexity. After we take over the trap table, we handle all PROM tlb misses fully. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Use sparc64_highest_unlocked_tlb_ent in __tsb_context_switch()David S. Miller2006-03-20
| | | | | | Instead of ugly hard-coded value. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix bogus flush instruction usage.David S. Miller2006-03-20
| | | | | | | | | | Some of the trap code was still assuming that alternate global %g6 was hard coded with current_thread_info(). Let's just consistently flush at KERNBASE when we need a pipeline synchronization. That's locked into the TLB and will always work. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix incorrect TSB lock bit handling.David S. Miller2006-03-20
| | | | | | | | | | The TSB_LOCK_BIT define is actually a special value shifted down by 32-bits for the assembler code macros. In C code, this isn't what we want. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill {save,restore}_alternate_globals()David S. Miller2006-03-20
| | | | | | | No longer needed now that we no longer have hard-coded alternate global register usage. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Preload TSB entries from update_mmu_cache().David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Dynamically grow TSB in response to RSS growth.David S. Miller2006-03-20
| | | | | | | | | As the RSS grows, grow the TSB in order to reduce the likelyhood of hash collisions and thus poor hit rates in the TSB. This definitely needs some serious tuning. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add infrastructure for dynamic TSB sizing.David S. Miller2006-03-20
| | | | | | | | | | | | | | | This also cleans up tsb_context_switch(). The assembler routine is now __tsb_context_switch() and the former is an inline function that picks out the bits from the mm_struct and passes it into the assembler code as arguments. setup_tsb_parms() computes the locked TLB entry to map the TSB. Later when we support using the physical address quad load instructions of Cheetah+ and later, we'll simply use the physical address for the TSB register value and set the map virtual and PTE both to zero. Signed-off-by: David S. Miller <davem@davemloft.net>
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