| Commit message (Collapse) | Author | Age |
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Signed-off-by: Philippe Gerum <rpm@xenomai.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Now that 0.1 of the BF51x is coming out, allow people to build for it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The BF526-EZBRD has a SST SPI flash on it, not a ST Micro.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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We read the SWRST (Software Reset) register to get at the last reset
state, and then we may configure the DOUBLE_FAULT bit to control behavior
when a double fault occurs. But if the lower bits of the register is
already set (like UART boot mode on a BF54x), we inadvertently make the
system reset by writing to the SYSTEM_RESET field at the same time. So
make sure the lower 4 bits are always cleared.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Split out the optional IRQ14 lowering code to further simplify the
asm_do_IRQ() function and keep the ifdef nest under control.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Take a page from x86 and abstract the stack checking out of the
asm_do_IRQ() function so that the result is easier to digest.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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With the common IRQ code initializing much more of the irq_desc state, we
can't blindly initialize it ourselves to the local bad_irq state. If we
do, we end up wrongly clobbering many fields. So punt most of the bad irq
code as the common layers will handle the default state, and simply call
handle_bad_irq() directly when the IRQ we are processing is invalid.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Update anomaly headers to match latest released anomaly sheets.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The BF533-EZKIT has two Flash In-System Programming devices hooked up to
the async memory bus, so add resources for the primary flashes and the
SRAMs on the devices.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The common DSA code changed structure layout, so update the BF518F-EZBRD
resources accordingly.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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The kgdb (in multiple places) and traps code developed pretty much
identical checks for how to access different regions of the Blackfin
memory map, but each wasn't 100%, so unify them to avoid duplication,
bitrot, and bugs with edge cases.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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* git://git.infradead.org/~dwmw2/iommu-2.6.31:
intel-iommu: Fix one last ia64 build problem in Pass Through Support
VT-d: support the device IOTLB
VT-d: cleanup iommu_flush_iotlb_psi and flush_unmaps
VT-d: add device IOTLB invalidation support
VT-d: parse ATSR in DMA Remapping Reporting Structure
PCI: handle Virtual Function ATS enabling
PCI: support the ATS capability
intel-iommu: dmar_set_interrupt return error value
intel-iommu: Tidy up iommu->gcmd handling
intel-iommu: Fix tiny theoretical race in write-buffer flush.
intel-iommu: Clean up handling of "caching mode" vs. IOTLB flushing.
intel-iommu: Clean up handling of "caching mode" vs. context flushing.
VT-d: fix invalid domain id for KVM context flush
Fix !CONFIG_DMAR build failure introduced by Intel IOMMU Pass Through Support
Intel IOMMU Pass Through Support
Fix up trivial conflicts in drivers/pci/{intel-iommu.c,intr_remapping.c}
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On ia64 with CONFIG_DMAR=n and CONFIG_SWIOTLB=y (as used in
arch/ia64/configs/tiger_defconfig) there is still a link
error with iommu_pass_through listed as an undefined symbol:
arch/ia64/kernel/built-in.o: In function `pci_swiotlb_init':
(.init.text+0x7f70): undefined reference to `iommu_pass_through'
Fix it by #defining iommu_pass_through away in asm/iommu.h
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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This updated patch should fix the compiling errors and remove the extern
iommu_pass_through from drivers/pci/intel-iommu.c file.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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The patch adds kernel parameter intel_iommu=pt to set up pass through
mode in context mapping entry. This disables DMAR in linux kernel; but
KVM still runs on VT-d and interrupt remapping still works.
In this mode, kernel uses swiotlb for DMA API functions but other VT-d
functionalities are enabled for KVM. KVM always uses multi level
translation page table in VT-d. By default, pass though mode is disabled
in kernel.
This is useful when people don't want to enable VT-d DMAR in kernel but
still want to use KVM and interrupt remapping for reasons like DMAR
performance concern or debug purpose.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Acked-by: Weidong Han <weidong@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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* git://git.infradead.org/mtd-2.6: (63 commits)
mtd: OneNAND: Allow setting of boundary information when built as module
jffs2: leaking jffs2_summary in function jffs2_scan_medium
mtd: nand: Fix memory leak on txx9ndfmc probe failure.
mtd: orion_nand: use burst reads with double word accesses
mtd/nand: s3c6400 support for s3c2410 driver
[MTD] [NAND] S3C2410: Use DIV_ROUND_UP
[MTD] [NAND] S3C2410: Deal with unaligned lengths in S3C2440 buffer read/write
[MTD] [NAND] S3C2410: Allow the machine code to get the BBT table from NAND
[MTD] [NAND] S3C2410: Added a kerneldoc for s3c2410_nand_set
mtd: physmap_of: Add multiple regions and concatenation support
mtd: nand: max_retries off by one in mxc_nand
mtd: nand: s3c2410_nand_setrate(): use correct macros for 2412/2440
mtd: onenand: add bbt_wait & unlock_all as replaceable for some platform
mtd: Flex-OneNAND support
mtd: nand: add OMAP2/OMAP3 NAND driver
mtd: maps: Blackfin async: fix memory leaks in probe/remove funcs
mtd: uclinux: mark local stuff static
mtd: uclinux: do not allow to be built as a module
mtd: uclinux: allow systems to override map addr/size
mtd: blackfin NFC: fix hang when using NAND on BF527-EZKITs
...
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Added a flag to allow the machine code to tell the NAND
subsystem that it should try to pickup a BBT from the flash,
and also skip the NAND full scan at startup.
Signed-off-by: Michel Pollet <buserror@gmail.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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Converted the old comnent to kerneldoc.
Signed-off-by: Michel Pollet <buserror@gmail.com>
[ben-linux@fluff.org: updated subject, spello fix]
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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checkpatch would complain with "disable_ecc : 1".
Signed-off-by: Nelson Castillo <arhuaco@freaks-unidos.net>
[ben-linux@fluff.org: subject cleanup]
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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Minimal support for the 4-bit ECC engine found on DM355, DM365,
DA830/OMAP-L137, and similar recent DaVinci-family chips.
This is limited to small-page flash for now; there are some page
layout issues for large page chips. Note that most boards using
this engine (like the DM355 EVM) include 2GiB large page chips.
Sanity tested on DM355 EVM after swapping the socketed NAND for
a small-page one.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (49 commits)
[ARM] idle: clean up pm_idle calling, obey hlt_counter
[ARM] S3C: Fix gpio-config off-by-one bug
[ARM] S3C64XX: add to_irq() support for EINT() GPIO
[ARM] S3C64XX: clock.c: fix typo in usb-host clock ctrlbit
[ARM] S3C64XX: fix HCLK gate defines
[ARM] Update mach-types
[ARM] wire up rt_tgsigqueueinfo and perf_counter_open
OMAP2 clock/powerdomain: off by 1 error in loop timeout comparisons
OMAP3 SDRC: set FIXEDDELAY when disabling SDRC DLL
OMAP3: Add support for DPLL3 divisor values higher than 2
OMAP3 SRAM: convert SRAM code to use macros rather than magic numbers
OMAP3 SRAM: add more comments on the SRAM code
OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change
OMAP3 clock: add a short delay when lowering CORE clk rate
OMAP3 clock: initialize SDRC timings at kernel start
OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize
[ARM] Add old Feroceon support to compressed/head.S
[ARM] 5559/1: Limit the stack unwinding caused by a kthread exit
[ARM] 5558/1: Add extra checks to ARM unwinder to avoid tracing corrupt stacks
[ARM] 5557/1: Discard some ARM.ex*.*exit.text sections when !HOTPLUG or !HOTPLUG_CPU
...
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pm_idle is used by infrastructure (eg, cpuidle) which expects architectures
to call it in a certain way. Arrange for ARM to follow x86's lead on this
and call pm_idle() with interrupts already disabled. However, we expect
pm_idle() to enable interrupts before it returns.
Also, OMAP wants to be able to disable hlt-ing, so allow hlt_counter to
prevent all calls to pm_idle.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Fix gpio-config off-by-one bug. Without this patch, touching GPA0 pin on
S3C64XX platform causes kernel oops.
Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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N group
Add to_irq() function to onvert gpio to irq for external interrupt
group (GPN).
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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The usb-host clock was using the wrong define (the SCLK enable for the
usb-host-bus) to change the HCLK register instead of the HCLK_UHOST bit.
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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A few typos seems to have sneaked into the HCLK gate defines, causing the
usb host clock to not get enabled. Fix them according to the reference
manual and throw in the 3d accel bit for good measure.
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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with while (i++ < MAX_CLOCK_ENABLE_WAIT); i can reach MAX_CLOCK_ENABLE_WAIT + 1
after the loop, so if (i == MAX_CLOCK_ENABLE_WAIT) that's still success.
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Correspondence with the TI OMAP hardware team indicates that
SDRC_DLLA_CTRL.FIXEDDELAY should be initialized to 0x0f. This number
was apparently derived from process validation. This is only used
when the SDRC DLL is unlocked (e.g., SDRC clock frequency less than
83MHz).
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Previously only 1 and 2 was supported. This is needed for DVFS VDD2 control.
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
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Convert omap3_sram_configure_core_dpll() to use macros rather than
magic numbers.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Clean up comments and copyrights on the CORE DPLL3 M2 divider change code.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Program the SDRC_MR_0 register as well during SDRC clock changes.
This register allows selection of the memory CAS latency. Some SDRAM
chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency
at lower clock rates.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2
divider, add a short delay before returning to SDRAM to allow the SDRC
time to stabilize. Without this delay, the system is prone to random
panics upon re-entering SDRAM.
This time delay varies based on MPU frequency. At 500MHz MPU frequency at
room temperature, 64 loops seems to work okay; so add another 32 loops for
environmental and process variation.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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On the OMAP3, initialize SDRC timings when the kernel boots. This ensures
that the kernel is running with known, optimized SDRC timings, rather than
whatever was configured by the bootloader.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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The original CDP kernel that this code comes from waited for 0x800
loops after switching the CORE DPLL M2 divider. This does not appear
to be necessary.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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This patch supports the cache handling for some old Feroceon cores for
which the CPU ID is like 0x41159260. This is a complement to
commit ab6d15d50637fc25ee941710b23fed09ceb28db3.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Not all Orion variants do implement the crypto unit.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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Without incrementing the counter the next window setup will overwrite
the SRAM mapping.
Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
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When a kthread function returns, it branches to do_exit(). However, the
unwinding information isn't valid anymore and any stack trace caused by
do_exit() may be incorrect. This patch adds a kernel_thread_exit()
function and annotated with '.cantunwind' so that the unwinder stops
when reaching it.
Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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There are situations where the unwinder goes beyond stack boundaries and
unwinds random data. This patch moves the stack boundaries check after
the unwind_exec_insn() call and adds an extra check for possible
infinite loops (like "mov pc, lr" with pc == lr).
The patch also fixes a bug in the unwind instructions interpreter. The
0xb0 instruction can only set PC to LR if this wasn't already set by
a previous instruction (this is used on exceptions taken while in kernel
mode where svc_entry is annotated with ".save {r0 - pc}").
Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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!HOTPLUG_CPU
Not discarding these sections when hotplug isn't available prevents the
kernel from building.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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From: Min Zhang <mzhang@mvista.com>
Add alignment fault fixup support for 32-bit Thumb-2 LDM, LDRD, POP,
PUSH, STM and STRD instructions. Alignment fault fixup support for
the remaining 32-bit Thumb-2 load/store instruction cases is not
included since ARMv6 and later processors include hardware support
for loads and stores of unaligned words and halfwords.
Signed-off-by: Min Zhang <mzhang@mvista.com>
Signed-off-by: George G. Davis <gdavis@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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The cpu member of struct irq_desc was recently renamed to node. The
patch renames the ARM references to the old member.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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