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* net: use NETDEV_TX_OK instead of 0 in ndo_start_xmit() functionsPatrick McHardy2009-07-05
| | | | | | | | | | | This patch is the result of an automatic spatch transformation to convert all ndo_start_xmit() return values of 0 to NETDEV_TX_OK. Some occurences are missed by the automatic conversion, those will be handled in a seperate patch. Signed-off-by: Patrick McHardy <kaber@trash.net> Signed-off-by: David S. Miller <davem@davemloft.net>
* Merge branch 'for-linus' of ↵Linus Torvalds2009-07-04
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kyle/parisc-2.6 * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kyle/parisc-2.6: (27 commits) parisc: use generic atomic64 on 32-bit parisc: superio: fix build breakage parisc: Fix PCI resource allocation on non-PAT SBA machines parisc: perf: wire up sys_perf_counter_open parisc: add task_pt_regs macro parisc: wire sys_perf_counter_open to sys_ni_syscall parisc: inventory.c, fix bloated stack frame parisc: processor.c, fix bloated stack frame parisc: fix compile warning in mm/init.c parisc: remove dead code from sys_parisc32.c parisc: wire up rt_tgsigqueueinfo parisc: ensure broadcast tlb purge runs single threaded parisc: fix "delay!" timer handling parisc: fix mismatched parenthesis in memcpy.c parisc: Fix gcc 4.4 warning in lba_pci.c parisc: add parameter to read_cr16() parisc: decode_exc.c should include kernel.h parisc: remove obsolete hw_interrupt_type parisc: fix irq compile bugs in arch/parisc/kernel/irq.c parisc: advertise PCI devs after "assign_resources" ... Manually fixed up trivial conflicts in tools/perf/perf.h due to addition of SH vs HPPA perf-counter support.
| * parisc: use generic atomic64 on 32-bitKyle McMartin2009-07-02
| | | | | | | | | | | | | | Somewhat redundant since our atomic_t uses hashed-locks on 32-bit anyway... Maybe we can clean those up to be generic too someday. Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
| * parisc: perf: wire up sys_perf_counter_openKyle McMartin2009-07-02
| | | | | | | | Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
| * parisc: add task_pt_regs macroKyle McMartin2009-07-02
| | | | | | | | | | | | needed for perf_counters. Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
| * parisc: wire sys_perf_counter_open to sys_ni_syscallKyle McMartin2009-07-02
| | | | | | | | | | | | Reserve a syscall slot for sys_perf_counter_open. Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
| * parisc: inventory.c, fix bloated stack frameKyle McMartin2009-07-02
| | | | | | | | | | | | | | The pa_pdc_cell struct can be kmalloc'd, so do that instead. Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
| * parisc: processor.c, fix bloated stack frameKyle McMartin2009-07-02
| | | | | | | | | | | | The pa_pdc_cell struct can be kmalloc'd, so do that instead. Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
| * parisc: fix compile warning in mm/init.cKyle McMartin2009-07-02
| | | | | | | | | | | | | | arch/parisc/mm/init.c: In function 'free_initmem': 381: warning: passing argument 1 of 'memset' makes pointer from integer without a cast Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
| * parisc: remove dead code from sys_parisc32.cChristoph Hellwig2009-07-02
| | | | | | | | | | | | | | | | | | Unless I'm totally missing something get_fd_set32/set_fd_set32 are completely unused. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
| * parisc: wire up rt_tgsigqueueinfoKyle McMartin2009-07-02
| | | | | | | | Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
| * parisc: ensure broadcast tlb purge runs single threadedHelge Deller2009-07-02
| | | | | | | | | | | | | | | | | | | | | | | | The TLB flushing functions on hppa, which causes PxTLB broadcasts on the system bus, needs to be protected by irq-safe spinlocks to avoid irq handlers to deadlock the kernel. The deadlocks only happened during I/O intensive loads and triggered pretty seldom, which is why this bug went so long unnoticed. Signed-off-by: Helge Deller <deller@gmx.de> [edited to use spin_lock_irqsave on UP as well since we'd been locking there all this time anyway, --kyle] Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
| * parisc: fix "delay!" timer handlingGrant Grundler2009-07-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rewrote timer_interrupt() to properly handle the "delayed!" case. If we used floating point math to compute the number of ticks that had elapsed since the last timer interrupt, it could take up to 12K cycles (emperical!) to handle the interrupt. Existing code assumed it would never take more than 8k cycles. We end up programming Interval Timer to a value less than "current" cycle counter. Thus have to wait until Interval Timer "wrapped" and would then get the "delayed!" printk that I moved below. Since we don't really know what the upper limit is, I prefer to read CR16 again after we've programmed it to make sure we won't have to wait for CR16 to wrap. Further, the printk was between reading CR16 (cycle couner) and writing CR16 (the interval timer). This would cause us to continue to set the interval timer to a value that was "behind" the cycle counter. Rinse and repeat. So no printk's between reading CR16 and setting next interval timer. Tested on A500 (550 Mhz PA8600). Signed-off-by: Grant Grundler <grundler@parisc-linux.org> Tested-by: Kyle McMartin <kyle@mcmartin.ca> Signed-off-by: Kyle McMartin <kyle@mcmartin.ca> ---- Kyle, Helge, and other parisc's, Please test on 32-bit before committing. I think I have it right but recognize I might not. TODO: I wanted to use "do_div()" in order to get both remainder and value back with one division op. That should help with the latency alot but can be applied seperately from this patch. thanks, grant
| * parisc: fix mismatched parenthesis in memcpy.cRandolph Chung2009-07-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | >>>> I think this is what was intended? Note that this patch may affect >>>> profiling. >>> it really should be >>> >>> - if (likely(t1 & (sizeof(unsigned int)-1)) == 0) { >>> + if (likely((t1 & (sizeof(unsigned int)-1)) == 0)) { >>> >>> randolph Reported-by: Roel Kluin <roel.kluin@gmail.com> Signed-off-by: Randolph Chung <tausq@parisc-linux.org> Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
| * parisc: add parameter to read_cr16()Coly Li2009-07-02
| | | | | | | | | | | | | | | | | | | | This patch modifies parameter of au1x_counter1_read() from 'void' to 'struct clocksource *cs', which fixes compile warning for incompatible parameter type. Signed-off-by: Coly Li <coly.li@suse.de> Signed-off-by: Helge Deller <deller@gmx.de> Cc: Ingo Molnar <mingo@elte.hu> Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
| * parisc: decode_exc.c should include kernel.hAlexander Beregalov2009-07-02
| | | | | | | | | | | | | | | | Fix this build error: arch/parisc/math-emu/decode_exc.c:351: undefined reference to `printk' Signed-off-by: Alexander Beregalov <a.beregalov@gmail.com> Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
| * parisc: remove obsolete hw_interrupt_typeThomas Gleixner2009-07-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The defines and typedefs (hw_interrupt_type, no_irq_type, irq_desc_t) have been kept around for migration reasons. After more than two years it's time to remove them finally. This patch cleans up one of the remaining users. When all such patches hit mainline we can remove the defines and typedefs finally. Impact: cleanup Convert the last remaining users to struct irq_chip and remove the define. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
| * parisc: fix irq compile bugs in arch/parisc/kernel/irq.cHelge Deller2009-07-02
| | | | | | | | | | | | | | | | | | | | | | Fix miscompilation in arch/parisc/kernel/irq.c: 123: warning: passing arg 1 of `cpumask_setall' from incompatible pointer type 141: warning: passing arg 1 of `cpumask_copy' from incompatible pointer type 300: warning: passing arg 1 of `cpumask_copy' from incompatible pointer type 357: warning: passing arg 2 of `cpumask_copy' from incompatible pointer type Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
| * parisc: fix ldcw inline assemblerHelge Deller2009-07-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two reasons to expose the memory *a in the asm: 1) To prevent the compiler from discarding a preceeding write to *a, and 2) to prevent it from caching *a in a register over the asm. The change has had a few days testing with a SMP build of 2.6.22.19 running on a rp3440. This patch is about the correctness of the __ldcw() macro itself. The use of the macro should be confined to small inline functions to try to limit the effect of clobbering memory on GCC's optimization of loads and stores. Signed-off-by: Dave Anglin <dave.anglin@nrc-cnrc.gc.ca> Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
| * parisc: kill WARN in free_initmem when DEBUG_KERNELKyle McMartin2009-07-02
| | | | | | | | | | | | | | | | Doing an IPI with local interrupts off triggers a warning. We don't need to be quite so ridiculously paranoid. Also, clean up a bit of the code a little. Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
| * parisc: Remove casts from atomic macrosBastian Blank2009-07-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The atomic operations on parisc are defined as macros. The macros includes casts which disallows the use of some syntax elements and produces error like this: net/phonet/pep.c: In function 'pipe_rcv_status': net/phonet/pep.c:262: error: lvalue required as left operand of assignment The patch removes this superfluous casts. Signed-off-by: Bastian Blank <waldi@debian.org> Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
| * parisc: remove CVS keywordsAlexander Beregalov2009-07-02
| | | | | | | | | | | | | | Signed-off-by: Alexander Beregalov <a.beregalov@gmail.com> Acked-by: Matthew Wilcox <willy@linux.intel.com> Acked-by: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
| * parisc: wire up preadv/pwritev syscallsKyle McMartin2009-07-02
| | | | | | | | | | | | Generic compat handlers look appropriate, so use those. Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
* | Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2009-07-04
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: MIPS: Fix CONFIG_FLATMEM version of pfn_valid() MIPS: Reorganize Cavium OCTEON PCI support. Update Yoichi Yuasa's e-mail address MIPS: Allow suspend and hibernation again on uniprocessor kernels. MIPS: 64-bit: Fix o32 core dump MIPS: BC47xx: Fix SSB irq setup MIPS: CMP: Update sync-r4k for current kernel MIPS: CMP: Move gcmp_probe to before the SMP ops MIPS: CMP: activate CMP support MIPS: CMP: Extend IPI handling to CPU number MIPS: CMP: Extend the GIC IPI interrupts beyond 32 MIPS: Define __arch_swab64 for all mips r2 cpus MIPS: Update VR41xx GPIO driver to use gpiolib MIPS: Hookup new syscalls sys_rt_tgsigqueueinfo and sys_perf_counter_open. MIPS: Malta: Remove unnecessary function prototypes MIPS: MT: Remove unnecessary semicolons MIPS: Add support for Texas Instruments AR7 System-on-a-Chip
| * | MIPS: Fix CONFIG_FLATMEM version of pfn_valid()Ralf Baechle2009-07-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For systems which do not define PHYS_OFFSET as 0 pfn_valid() may falsely have returned 0 on most configurations. Bug introduced by commit 752fbeb2e3555c0d236e992f1195fd7ce30e728d (linux-mips.org) rsp. 6f284a2ce7b8bc49cb8455b1763357897a899abb (kernel.org) titled "[MIPS] FLATMEM: introduce PHYS_OFFSET." Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Reorganize Cavium OCTEON PCI support.David Daney2009-07-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move the cavium PCI files to the arch/mips/pci directory. Also cleanup comment formatting and code layout. Code from pci-common.c, was moved into other files. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | Update Yoichi Yuasa's e-mail addressYoichi Yuasa2009-07-03
| | | | | | | | | | | | | | | Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Allow suspend and hibernation again on uniprocessor kernels.Ralf Baechle2009-07-03
| | | | | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: Pavel Machek <pavel@ucw.cz>
| * | MIPS: 64-bit: Fix o32 core dumpYong Zhang2009-07-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If an o32 process generates a core dump on a 64 bit kernel, the core file will not be correctly recognized. This is because ELF_CORE_COPY_REGS and ELF_CORE_COPY_TASK_REGS are not correctly defined for o32 and will use the default register set which would be CONFIG_64BIT in asm/elf.h. So we'll switch to use the right register defines in this situation by checking for WANT_COMPAT_REG_H and use the right defines of ELF_CORE_COPY_REGS and ELF_CORE_COPY_TASK_REGS. [Ralf: made ELF_CORE_COPY_TASK_REGS() bullet-proof against funny arguments.] Signed-off-by: Yong Zhang <yong.zhang@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: CMP: Update sync-r4k for current kernelTim Anderson2009-07-03
| | | | | | | | | | | | | | | | | | | | | | | | This revises the sync-4k so it will boot and operate since the removal of expirelo from the timer code. Signed-off-by: Tim Anderson <tanderson@mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: CMP: Move gcmp_probe to before the SMP opsTim Anderson2009-07-03
| | | | | | | | | | | | | | | | | | | | | | | | This is to move the gcmp_probe call to before the use of and selection of the smp_ops functions. This allows malta with 1004K to work. Signed-off-by: Tim Anderson <tanderson@mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: CMP: activate CMP supportTim Anderson2009-07-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the CMP support was added before, this mostly correct compile problems but adds a platform specific translation for the interrupt number based on cpu number. Signed-off-by: Tim Anderson <tanderson@mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: CMP: Extend IPI handling to CPU numberTim Anderson2009-07-03
| | | | | | | | | | | | | | | | | | | | | | | | This takes the current IPI interrupt assignment from the fix number of 4 to the number of CPUs defined in the system. Signed-off-by: Tim Anderson <tanderson@mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: CMP: Extend the GIC IPI interrupts beyond 32Tim Anderson2009-07-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch extends the GIC interrupt handling beyond the current 32 bit range as well as extending the number of interrupts based on the number of CPUs. Signed-off-by: Tim Anderson <tanderson@mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Define __arch_swab64 for all mips r2 cpusDavid Daney2009-07-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some CPUs implement mipsr2, but because they are a super-set of mips64r2 do not define CONFIG_CPU_MIPS64_R2. Cavium OCTEON falls into this category. We would still like to use the optimized implementation, so since we have already checked for CONFIG_CPU_MIPSR2, checking for CONFIG_64BIT instead of CONFIG_CPU_MIPS64_R2 is sufficient. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Update VR41xx GPIO driver to use gpiolibYoichi Yuasa2009-07-03
| | | | | | | | | | | | | | | Signed-off-by: Yoichi Yuasa <yyuasa@linux.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Hookup new syscalls sys_rt_tgsigqueueinfo and sys_perf_counter_open.David Daney2009-07-03
| | | | | | | | | | | | | | | | | | | | | [Ralf: I fixed up the numbering in the comment in scall64-n32.S.] Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Malta: Remove unnecessary function prototypesDmitri Vorobiev2009-07-03
| | | | | | | | | | | | | | | Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: MT: Remove unnecessary semicolonsJoe Perches2009-07-03
| | | | | | | | | | | | | | | Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Add support for Texas Instruments AR7 System-on-a-ChipFlorian Fainelli2009-07-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the Texas Instruments AR7 System-on-a-Chip. It supports the TNETD7100, 7200 and 7300 versions of the SoC. Signed-off-by: Matteo Croce <matteo@openwrt.org> Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: Eugene Konev <ejka@openwrt.org> Signed-off-by: Nicolas Thill <nico@openwrt.org> Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | Merge git://git.kernel.org/pub/scm/linux/kernel/git/sam/kbuild-fixesLinus Torvalds2009-07-04
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/sam/kbuild-fixes: kbuild: finally remove the obsolete variable $TOPDIR gitignore: ignore scripts/ihex2fw Kbuild: Disable the -Wformat-security gcc flag gitignore: ignore gcov output files kbuild: deb-pkg ship changelog Add new __init_task_data macro to be used in arch init_task.c files. asm-generic/vmlinux.lds.h: shuffle INIT_TASK* macro names in vmlinux.lds.h Add new macros for page-aligned data and bss sections. asm-generic/vmlinux.lds.h: Fix up RW_DATA_SECTION definition.
| * | | asm-generic/vmlinux.lds.h: shuffle INIT_TASK* macro names in vmlinux.lds.hTim Abbott2009-06-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We recently added a INIT_TASK(align) in include/asm-generic/vmlinux.lds.h, but there is already a macro INIT_TASK in include/linux/init_task.h, which is quite confusing. We should switch the macro in the linker script to INIT_TASK_DATA. (Sorry that I missed this in reviewing the patch). Since the macros are new, there is only one user of the INIT_TASK in vmlinux.lds.h, arch/mn10300/kernel/vmlinux.lds.S. However, we are currently using INIT_TASK_DATA for laying down an entire .data.init_task section. So rename that to INIT_TASK_DATA_SECTION. I would be worried about changing the meaning of INIT_TASK_DATA, but the old INIT_TASK_DATA implementation had no users, and in fact if anyone had tried to use it, it would have failed to compile because it didn't pass the alignment to the old INIT_TASK. Signed-off-by: Tim Abbott <tabbott@ksplice.com> Cc: David Howells <dhowells@redhat.com> Cc: Jesper Nilsson <Jesper.Nilsson@axis.com Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
* | | | Merge git://git.infradead.org/iommu-2.6Linus Torvalds2009-07-02
|\ \ \ \ | |_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.infradead.org/iommu-2.6: (38 commits) intel-iommu: Don't keep freeing page zero in dma_pte_free_pagetable() intel-iommu: Introduce first_pte_in_page() to simplify PTE-setting loops intel-iommu: Use cmpxchg64_local() for setting PTEs intel-iommu: Warn about unmatched unmap requests intel-iommu: Kill superfluous mapping_lock intel-iommu: Ensure that PTE writes are 64-bit atomic, even on i386 intel-iommu: Make iommu=pt work on i386 too intel-iommu: Performance improvement for dma_pte_free_pagetable() intel-iommu: Don't free too much in dma_pte_free_pagetable() intel-iommu: dump mappings but don't die on pte already set intel-iommu: Combine domain_pfn_mapping() and domain_sg_mapping() intel-iommu: Introduce domain_sg_mapping() to speed up intel_map_sg() intel-iommu: Simplify __intel_alloc_iova() intel-iommu: Performance improvement for domain_pfn_mapping() intel-iommu: Performance improvement for dma_pte_clear_range() intel-iommu: Clean up iommu_domain_identity_map() intel-iommu: Remove last use of PHYSICAL_PAGE_MASK, for reserving PCI BARs intel-iommu: Make iommu_flush_iotlb_psi() take pfn as argument intel-iommu: Change aligned_size() to aligned_nrpages() intel-iommu: Clean up intel_map_sg(), remove domain_page_mapping() ...
| * | | intel-iommu: Make iommu=pt work on i386 tooDavid Woodhouse2009-07-01
| | | | | | | | | | | | | | | | Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * | | intel-iommu: Clean up identity mapping code, remove CONFIG_DMAR_GFX_WADavid Woodhouse2009-06-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no need for the GFX workaround now we have 'iommu=pt' for the cases where people really care about performance. There's no need to have a special case for just one type of device. This also speeds up the iommu=pt path and reduces memory usage by setting up the si_domain _once_ and then using it for all devices, rather than giving each device its own private page tables. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* | | | x86: add boundary check for 32bit res before expand e820 resource to alignmentYinghai Lu2009-07-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fix hang with HIGHMEM_64G and 32bit resource. According to hpa and Linus, use (resource_size_t)-1 to fend off big ranges. Analyzed by hpa Reported-and-tested-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | | x86: fix power-of-2 round_up/round_down macrosLinus Torvalds2009-07-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These macros had two bugs: - the type of the mask was not correctly expanded to the full size of the argument being expanded, resulting in possible loss of high bits when mixing types. - the alignment argument was evaluated twice, despite the macro looking like a fancy function (but it really does need to be a macro, since it works on arbitrary integer types) Noticed by Peter Anvin, and with a fix that is a modification of his suggestion (bug noticed by Yinghai Lu). Cc: Peter Anvin <hpa@zytor.com> Cc: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | | FRV: Add basic performance counter supportDavid Howells2009-07-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic performance counter support to the FRV arch. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | | FRV: Implement atomic64_tDavid Howells2009-07-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement atomic64_t and its ops for FRV. Tested with the following patch: diff --git a/arch/frv/kernel/setup.c b/arch/frv/kernel/setup.c index 55e4fab..086d50d 100644 --- a/arch/frv/kernel/setup.c +++ b/arch/frv/kernel/setup.c @@ -746,6 +746,52 @@ static void __init parse_cmdline_early(char *cmdline) } /* end parse_cmdline_early() */ +static atomic64_t xxx; + +static void test_atomic64(void) +{ + atomic64_set(&xxx, 0x12300000023LL); + + mb(); + BUG_ON(atomic64_read(&xxx) != 0x12300000023LL); + mb(); + if (atomic64_inc_return(&xxx) != 0x12300000024LL) + BUG(); + mb(); + BUG_ON(atomic64_read(&xxx) != 0x12300000024LL); + mb(); + if (atomic64_sub_return(0x36900000050LL, &xxx) != -0x2460000002cLL) + BUG(); + mb(); + BUG_ON(atomic64_read(&xxx) != -0x2460000002cLL); + mb(); + if (atomic64_dec_return(&xxx) != -0x2460000002dLL) + BUG(); + mb(); + BUG_ON(atomic64_read(&xxx) != -0x2460000002dLL); + mb(); + if (atomic64_add_return(0x36800000001LL, &xxx) != 0x121ffffffd4LL) + BUG(); + mb(); + BUG_ON(atomic64_read(&xxx) != 0x121ffffffd4LL); + mb(); + if (atomic64_cmpxchg(&xxx, 0x123456789abcdefLL, 0x121ffffffd4LL) != 0x121ffffffd4LL) + BUG(); + mb(); + BUG_ON(atomic64_read(&xxx) != 0x121ffffffd4LL); + mb(); + if (atomic64_cmpxchg(&xxx, 0x121ffffffd4LL, 0x123456789abcdefLL) != 0x121ffffffd4LL) + BUG(); + mb(); + BUG_ON(atomic64_read(&xxx) != 0x123456789abcdefLL); + mb(); + if (atomic64_xchg(&xxx, 0xabcdef123456789LL) != 0x123456789abcdefLL) + BUG(); + mb(); + BUG_ON(atomic64_read(&xxx) != 0xabcdef123456789LL); + mb(); +} + /*****************************************************************************/ /* * @@ -845,6 +891,8 @@ void __init setup_arch(char **cmdline_p) // asm volatile("movgs %0,timerd" :: "r"(10000000)); // __set_HSR(0, __get_HSR(0) | HSR0_ETMD); + test_atomic64(); + } /* end setup_arch() */ #if 0 Note that this doesn't cover all the trivial wrappers, but does cover all the substantial implementations. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | | Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6Linus Torvalds2009-07-01
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: sh: LCDC dcache flush for deferred io sh: Fix compiler error and include the definition of IS_ERR_VALUE sh: re-add LCDC fbdev support to the Migo-R defconfig sh: fix se7724 ceu names sh: ms7724se: Enable sh_eth in defconfig. arch/sh/boards/mach-se/7206/io.c: Remove unnecessary semicolons sh: ms7724se: Add sh_eth support nommu: provide follow_pfn(). sh: Kill off unused DEBUG_BOOTMEM symbol. perf_counter tools: add cpu_relax()/rmb() definitions for sh. sh64: Hook up page fault events for software perf counters. sh: Hook up page fault events for software perf counters. sh: make set_perf_counter_pending() static inline. clocksource: sh_tmu: Make undefined TCOR behaviour less undefined.
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