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* MIPS: Allow UserLocal on MIPS_R1 processorsKevin Cernekee2010-10-29
| | | | | | | | | | Some MIPS32R1 processors implement UserLocal (RDHWR $29) to accelerate programs that make extensive use of thread-local storage. Therefore, setting up the HWRENA register should not depend on cpu_has_mips_r2. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
* MIPS: Honor L2 bypass bitKevin Cernekee2010-10-29
| | | | | | | | | | | | | | | | On many of the newer MIPS32 cores, CP0 CONFIG2 bit 12 (L2B) indicates that the L2 cache is disabled and therefore Linux should not attempt to use it. [Ralf: Moved the code added by Kevin's original patch into a separate function that can easily be replaced for platforms that need more a different probe.] Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org> Cc: <linux-kernel@vger.kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/1723/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add BMIPS CP0 register definitionsKevin Cernekee2010-10-29
| | | | | | | | | | Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: mbizon@freebox.fr Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Tested-by: Florian Fainelli <ffainelli@freebox.fr> Patchwork: https://patchwork.linux-mips.org/patch/1708/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org
* MIPS: Add BMIPS processor types to KconfigKevin Cernekee2010-10-29
| | | | | | | | | | | | | | | [v2: add "VIPER" marketing name for BMIPS4350] Add processor feature definitions for BMIPS3300, BMIPS4350, BMIPS4380, and BMIPS5000. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: mbizon@freebox.fr Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Tested-by: Florian Fainelli <ffainelli@freebox.fr> Patchwork: https://patchwork.linux-mips.org/patch/1716/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org
* MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC codeKevin Cernekee2010-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | BMIPS processor cores are used in 50+ different chipsets spread across 5+ product lines. In many cases the chipsets do not share the same peripheral register layouts, the same register blocks, the same interrupt controllers, the same memory maps, or much of anything else. But, across radically different SoCs that share nothing more than the same BMIPS CPU, a few things are still mostly constant: SMP operations Access to performance counters DMA cache coherency quirks Cache and memory bus configuration So, it makes sense to treat each BMIPS processor type as a generic "building block," rather than tying it to a specific SoC. This makes it easier to support a large number of BMIPS-based chipsets without unnecessary duplication of code, and provides the infrastructure needed to support BMIPS-proprietary features. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: mbizon@freebox.fr Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Tested-by: Florian Fainelli <ffainelli@freebox.fr> Patchwork: https://patchwork.linux-mips.org/patch/1706/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org
* MIPS: Add support for hardware performance events (mipsxx)Deng-Cheng Zhu2010-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the mipsxx Perf-events support based on the skeleton. Generic hardware events and cache events are now fully implemented for the 24K/34K/74K/1004K cores. To support other cores in mipsxx (such as R10000/SB1), the generic hardware event tables and cache event tables need to be filled out. To support other CPUs which have different PMU than mipsxx, such as RM9000 and LOONGSON2, the additional files perf_event_$cpu.c need to be created. Raw event is an important part of Perf-events. It helps the user collect performance data for events that are not listed as the generic hardware events and cache events but ARE supported by the CPU's PMU. This patch also adds this feature for mipsxx 24K/34K/74K/1004K. For how to use it, please refer to processor core software user's manual and the comments for mipsxx_pmu_map_raw_event() for more details. Please note that this is a "precise" implementation, which means the kernel will check whether the requested raw events are supported by this CPU and which hardware counters can be assigned for them. To test the functionality of Perf-event, you may want to compile the tool "perf" for your MIPS platform. You can refer to the following URL: http://www.linux-mips.org/archives/linux-mips/2010-10/msg00126.html You also need to customize the CFLAGS and LDFLAGS in tools/perf/Makefile for your libs, includes, etc. In case you encounter the boot failure in SMVP kernel on multi-threading CPUs, you may take a look at: http://www.linux-mips.org/git?p=linux-mti.git;a=commitdiff;h=5460815027d802697b879644c74f0e8365254020 Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Cc: ddaney@caviumnetworks.com Cc: matt@console-pimps.org Patchwork: https://patchwork.linux-mips.org/patch/1689/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/kernel/perf_event_mipsxx.c
* MIPS: Perf-events: Add callchain supportDeng-Cheng Zhu2010-10-29
| | | | | | | | | | | | | | | | | | | | | Adds callchain support for MIPS Perf-events. For more info on this feature, please refer to tools/perf/Documentation/perf-report.txt and tools/perf/design.txt. Currently userspace callchain data is not recorded, because we do not have a safe way to do this. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> Acked-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Cc: matt@console-pimps.org Patchwork: https://patchwork.linux-mips.org/patch/1690/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: add support for hardware performance events (skeleton)Deng-Cheng Zhu2010-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides the skeleton of the HW perf event support. To enable this feature, we can not choose the SMTC kernel; Oprofile should be disabled; kernel performance events be selected. Then we can enable it in Kernel type menu. Oprofile for MIPS platforms initializes irq at arch init time. Currently we do not change this logic to allow PMU reservation. If a platform has EIC, we can use the irq base and perf counter irq offset defines for the interrupt controller in specific init_hw_perf_events(). Based on this skeleton patch, the 3 different kinds of MIPS PMU, namely, mipsxx/loongson2/rm9000, can be supported by adding corresponding lower level C files at the bottom. The suggested names of these files are perf_event_mipsxx.c/perf_event_loongson2.c/perf_event_rm9000.c. So, for example, we can do this by adding "#include perf_event_mipsxx.c" at the bottom of perf_event.c. In addition, PMUs with 64bit counters are also considered in this patch. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Cc: ddaney@caviumnetworks.com Cc: matt@console-pimps.org Patchwork: https://patchwork.linux-mips.org/patch/1688/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: add support for software performance eventsDeng-Cheng Zhu2010-10-29
| | | | | | | | | | | | | | | | | | | | | | | Software events are required as part of the measurable stuff by the Linux performance counter subsystem. Here is the list of events added by this patch: PERF_COUNT_SW_PAGE_FAULTS PERF_COUNT_SW_PAGE_FAULTS_MIN PERF_COUNT_SW_PAGE_FAULTS_MAJ PERF_COUNT_SW_ALIGNMENT_FAULTS PERF_COUNT_SW_EMULATION_FAULTS Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Acked-by: David Daney <ddaney@caviumnetworks.com> Reviewed-by: Matt Fleming <matt@console-pimps.org> Patchwork: https://patchwork.linux-mips.org/patch/1686/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: define local_xchg from xchg_local to atomic_long_xchgDeng-Cheng Zhu2010-10-29
| | | | | | | | | | | | | | | | | | | Perf-events is now using local_t helper functions internally. There is a use of local_xchg(). On MIPS, this is defined to xchg_local() which is missing in asm/system.h. This patch re-defines local_xchg() in asm/local.h to atomic_long_xchg(). Then Perf-events can pass the build. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Cc: ddaney@caviumnetworks.com Cc: matt@console-pimps.org Patchwork: https://patchwork.linux-mips.org/patch/1687/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: AR7: Add support for Titan (TNETV10xx) SoC variantFlorian Fainelli2010-10-29
| | | | | | | | | | | | | | | | | | | Add support for Titan TNETV1050,1055,1056,1060 variants. This SoC is almost completely identical to AR7 except on a few points: - a second bank of gpios is available - vlynq0 on titan is vlynq1 on ar7 - different PHY addresses for cpmac0 This SoC can be found on commercial products like the Linksys WRTP54G Original patch by Xin with improvments by Florian. Signed-off-by: Xin Zhen <xlonestar2000@aim.com> Signed-off-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/1563/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
* MIPS: AR7: Initialize GPIO earlierFlorian Fainelli2010-10-29
| | | | | | | | | | | In order to detect the Titan variant, we must initialize GPIOs earlier since detection relies on some GPIO values to be set. Signed-off-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/1562/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
* MIPS: Add platform device and Kconfig for Octeon USB EHCI / OHCIDavid Daney2010-10-29
| | | | | | | | | | | | | Declare that OCTEON reference boards have both OHCI and EHCI. Add platform devices for the corresponding hardware. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-usb@vger.kernel.org To: dbrownell@users.sourceforge.net Patchwork: http://patchwork.linux-mips.org/patch/1676/ Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Add register definitions for EHCI / OHCI USB glue logic.David Daney2010-10-29
| | | | | | | | | | | | | | The EHCI and OHCI blocks connection to the I/O bus is controlled by these registers. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-usb@vger.kernel.org To: dbrownell@users.sourceforge.net Patchwork: http://patchwork.linux-mips.org/patch/1674/ Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
* MIPS: Octeon: Apply CN63XXP1 errata workarounds.David Daney2010-10-29
| | | | | | | | | | | | | | | The CN63XXP1 needs a couple of workarounds to ensure memory is not written in unexpected ways. All PREF with hints in the range 0-4,6-24 are replaced with PREF 28. We pass a flag to the assembler to cover compiler generated code, and patch uasm for the dynamically generated code. The write buffer threshold is reduced to 4. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1672/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Use I/O clock rate for calculations.David Daney2010-10-29
| | | | | | | | | The I2C and UARTS are clocked by the I/O clock, use its rate for these devices. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1670/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Add octeon_get_io_clock_rate() for cn63xxDavid Daney2010-10-29
| | | | | | | | | | | | | Starting with cn63xx Octeon I/O blocks are clocked at a different rate than the CPU. Add a new function octeon_get_io_clock_rate() that yields the I/O clock rate. Also rearrange octeon_get_clock_rate() to get the value from the saved sysinfo structure. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1671/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Remove bogus code from octeon_get_clock_rate()David Daney2010-10-29
| | | | | | | | | We can run with any simulator clock rate. Get rid of the code overriding it to 6MHz. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1669/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Scale Octeon2 clocks in octeon_init_cvmcount()David Daney2010-10-29
| | | | | | | | | The per-CPU clocks are synchronized from IPD_CLK_COUNT, on cn63XX it must be scaled by the clock frequency ratio. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1667/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Enable Read Inhibit / eXecute Inhibit on Octeon II.David Daney2010-10-29
| | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1666/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Probe for Octeon II CPUs.David Daney2010-10-29
| | | | | | | | | | The OCTEON II ISA extends the original OCTEON ISA, so give it its own __elf_platform string so optimized libraries can be selected in userspace. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1665/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Handle Octeon II caches.David Daney2010-10-29
| | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1664/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add identifiers for Octeon II CPUs.David Daney2010-10-29
| | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1662/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Update L2 Cache code for CN63XXDavid Daney2010-10-29
| | | | | | | | | | | | The CN63XX has a different L2 cache architecture. Update the helper functions to reflect this. Some joining of split lines was also done to improve readability, as well as reformatting of comments. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1663/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Add cn63XX to Octeon chip detection macros.David Daney2010-10-29
| | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1661/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Update register definitions for CN63XX chipsDavid Daney2010-10-29
| | | | | | | | | | | The CN63XX is a new 6-CPU SOC based on the new OCTEON II CPU cores. Join some lines back together. This makes some of them exceed 80 columns, but they are uninteresting and this unclutters things. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1668/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Rewrite DMA mapping functions.David Daney2010-10-29
| | | | | | | | | | | | | All Octeon chips can support more than 4GB of RAM. Also due to how Octeon PCI is setup, even some configurations with less than 4GB of RAM will have portions that are not accessible from 32-bit devices. Enable the swiotlb code to handle the cases where a device cannot directly do DMA. This is a complete rewrite of the Octeon DMA mapping code. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1639/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add a platform hook for swiotlb setup.David Daney2010-10-29
| | | | | | | | This allows platforms that are using the swiotlb to initialize it. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1638/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Convert DMA to use dma-mapping-common.hDavid Daney2010-10-29
| | | | | | | | | | | | | | | | | | | | Use asm-generic/dma-mapping-common.h to handle all DMA mapping operations and establish a default get_dma_ops() that forwards all operations to the existing code. Augment dev_archdata to carry a pointer to the struct dma_map_ops, allowing DMA operations to be overridden on a per device basis. Currently this is never filled in, so the default dma_map_ops are used. A follow-on patch sets this for Octeon PCI devices. Also initialize the dma_debug system as it is now used if it is configured. Includes fixes by Kevin Cernekee <cernekee@gmail.com>. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1637/ Patchwork: http://patchwork.linux-mips.org/patch/1678/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ip32, ip27, jazz: Make static functions in dma-coherence.h inline.David Daney2010-10-29
| | | | | | | | | | Any function defined in a header file should be inline. This helps us avoid 'unused' compiler warnings when we include the files in more places in subsequent patches. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1636/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Select ZONE_DMA32David Daney2010-10-29
| | | | | | | | Give us a nice place to allocate coherent DMA memory for 32-bit devices. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1635/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Adjust top of DMA32 zone.David Daney2010-10-29
| | | | | | | | | | On OCTEON, we reserve the last 256MB of 32-bit PCI address space, mapping the RAM in this region at a high DMA address. This makes memory in this region unavailable for 32-bit DMA. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1634/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Allow MAX_DMA32_PFN to be overridden.David Daney2010-10-29
| | | | | | | | | DMA mapping may reduce the usable physical address range usable for 32-bit DMA. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1633/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Set dma_masks for octeon_mgmt device.David Daney2010-10-29
| | | | | | | | | This allows follow-on patches to dma mapping functions to work with the octeon mgmt device.. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1632/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: IRQ: Add stackoverflow detectionFrom: jiang.adam@gmail.com2010-10-29
| | | | | | | | | | | | | | | | | | | Add stackoverflow detection to mips arch Signed-off-by: Adam Jiang <jiang.adam@gmail.com> Cc: dmitri.vorobiev@movial.com Cc: wuzhangjin@gmail.com Cc: ddaney@caviumnetworks.com Cc: peterz@infradead.org Cc: fweisbec@gmail.com Cc: tj@kernel.org Cc: tglx@linutronix.de Cc: mingo@elte.hu Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1559/ Patchwork: https://patchwork.linux-mips.org/patch/1651/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Kconfig cleanupThomas Gleixner2010-10-29
| | | | | | | | arch/mips/Kconfig already sets GENERIC_HARDIRQS_NO__DO_IRQ unconditionally. Remove the redundant select from the Loongson Kconfig. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove wait argument of r4k_on_each_cpuRalf Baechle2010-10-29
| | | | | | All callers were passing in 1 anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: More detailed description of r4k_on_each_cpuRalf Baechle2010-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Get rid of branches to .subsections.Ralf Baechle2010-10-29
| | | | | | | | | | | | | | | | | | | | | | | | It was a nice optimization - on paper at least. In practice it results in branches that may exceed the maximum legal range for a branch. We can fight that problem with -ffunction-sections but -ffunction-sections again is incompatible with -pg used by the function tracer. By rewriting the loop around all simple LL/SC blocks to C we reduce the amount of inline assembler and at the same time allow GCC to often fill the branch delay slots with something sensible or whatever else clever optimization it may have up in its sleeve. With this optimization gone we also no longer need -ffunction-sections, so drop it. This optimization was originally introduced in 2.6.21, commit 5999eca25c1fd4b9b9aca7833b04d10fe4bc877d (linux-mips.org) rsp. f65e4fa8e0c6022ad58dc88d1b11b12589ed7f9f (kernel.org). Original fix for the issues which caused me to pull this optimization by Paul Gortmaker <paul.gortmaker@windriver.com>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'stable/xen-pcifront-0.8.2' of ↵Linus Torvalds2010-10-28
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen and branch 'for-linus' of git://xenbits.xen.org/people/sstabellini/linux-pvhvm * 'for-linus' of git://xenbits.xen.org/people/sstabellini/linux-pvhvm: xen: register xen pci notifier xen: initialize cpu masks for pv guests in xen_smp_init xen: add a missing #include to arch/x86/pci/xen.c xen: mask the MTRR feature from the cpuid xen: make hvc_xen console work for dom0. xen: add the direct mapping area for ISA bus access xen: Initialize xenbus for dom0. xen: use vcpu_ops to setup cpu masks xen: map a dummy page for local apic and ioapic in xen_set_fixmap xen: remap MSIs into pirqs when running as initial domain xen: remap GSIs as pirqs when running as initial domain xen: introduce XEN_DOM0 as a silent option xen: map MSIs into pirqs xen: support GSI -> pirq remapping in PV on HVM guests xen: add xen hvm acpi_register_gsi variant acpi: use indirect call to register gsi in different modes xen: implement xen_hvm_register_pirq xen: get the maximum number of pirqs from xen xen: support pirq != irq * 'stable/xen-pcifront-0.8.2' of git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen: (27 commits) X86/PCI: Remove the dependency on isapnp_disable. xen: Update Makefile with CONFIG_BLOCK dependency for biomerge.c MAINTAINERS: Add myself to the Xen Hypervisor Interface and remove Chris Wright. x86: xen: Sanitse irq handling (part two) swiotlb-xen: On x86-32 builts, select SWIOTLB instead of depending on it. MAINTAINERS: Add myself for Xen PCI and Xen SWIOTLB maintainer. xen/pci: Request ACS when Xen-SWIOTLB is activated. xen-pcifront: Xen PCI frontend driver. xenbus: prevent warnings on unhandled enumeration values xenbus: Xen paravirtualised PCI hotplug support. xen/x86/PCI: Add support for the Xen PCI subsystem x86: Introduce x86_msi_ops msi: Introduce default_[teardown|setup]_msi_irqs with fallback. x86/PCI: Export pci_walk_bus function. x86/PCI: make sure _PAGE_IOMAP it set on pci mappings x86/PCI: Clean up pci_cache_line_size xen: fix shared irq device passthrough xen: Provide a variant of xen_poll_irq with timeout. xen: Find an unbound irq number in reverse order (high to low). xen: statically initialize cpu_evtchn_mask_p ... Fix up trivial conflicts in drivers/pci/Makefile
| * xen: initialize cpu masks for pv guests in xen_smp_initStefano Stabellini2010-10-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Pv guests don't have ACPI and need the cpu masks to be set correctly as early as possible so we call xen_fill_possible_map from xen_smp_init. On the other hand the initial domain supports ACPI so in this case we skip xen_fill_possible_map and rely on it. However Xen might limit the number of cpus usable by the domain, so we filter those masks during smp initialization using the VCPUOP_is_up hypercall. It is important that the filtering is done before xen_setup_vcpu_info_placement. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
| * xen: add a missing #include to arch/x86/pci/xen.cStefano Stabellini2010-10-22
| | | | | | | | | | | | Add missing #include <asm/io_apic.h> to arch/x86/pci/xen.c. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
| * xen: mask the MTRR feature from the cpuidStefano Stabellini2010-10-22
| | | | | | | | | | | | | | | | | | We don't want Linux to think that the cpu supports MTRRs when running under Xen because MTRR operations could only be performed through hypercalls. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
| * xen: add the direct mapping area for ISA bus accessJuan Quintela2010-10-22
| | | | | | | | | | | | | | | | | | | | add the direct mapping area for ISA bus access when running as initial domain Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
| * xen: use vcpu_ops to setup cpu masksStefano Stabellini2010-10-22
| | | | | | | | | | Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
| * xen: map a dummy page for local apic and ioapic in xen_set_fixmapJeremy Fitzhardinge2010-10-22
| | | | | | | | | | | | Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
| * xen: remap MSIs into pirqs when running as initial domainQing He2010-10-22
| | | | | | | | | | | | | | | | | | | | | | | | Implement xen_create_msi_irq to create an msi and remap it as pirq. Use xen_create_msi_irq to implement an initial domain specific version of setup_msi_irqs. Signed-off-by: Qing He <qing.he@intel.com> Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com> Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
| * xen: remap GSIs as pirqs when running as initial domainJeremy Fitzhardinge2010-10-22
| | | | | | | | | | | | | | | | | | | | | | | | Implement xen_register_gsi to setup the correct triggering and polarity properties of a gsi. Implement xen_register_pirq to register a particular gsi as pirq and receive interrupts as events. Call xen_setup_pirqs to register all the legacy ISA irqs as pirqs. Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
| * xen: introduce XEN_DOM0 as a silent optionStefano Stabellini2010-10-22
| | | | | | | | | | | | | | | | | | Add XEN_DOM0 to arch/x86/xen/Kconfig as a silent compile time option that gets enabled when xen and basic x86, acpi and pci support are selected. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
| * xen: map MSIs into pirqsStefano Stabellini2010-10-22
| | | | | | | | | | | | | | | | Map MSIs into pirqs, writing 0 in the MSI vector data field and the pirq number in the MSI destination id field. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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