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* Merge git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6Linus Torvalds2007-05-07
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6: [IA64] update memory attribute aliasing documentation & test cases [IA64] fail mmaps that span areas with incompatible attributes [IA64] allow WB /sys/.../legacy_mem mmaps [IA64] make ioremap avoid unsupported attributes [IA64] rename ioremap variables to match i386 [IA64] relax per-cpu TLB requirement to DTC [IA64] remove per-cpu ia64_phys_stacked_size_p8 [IA64] Fix example error injection program [IA64] Itanium MC Error Injection Tool: pal_mc_error_inject() interface [IA64] Itanium MC Error Injection Tool: Makefile changes [IA64] Itanium MC Error Injection Tool: Driver sysfs interface [IA64] Itanium MC Error Injection Tool: Doc and sample application [IA64] Itanium MC Error Injection Tool: Kernel configuration
| * Pull mem-attribute into release branchTony Luck2007-04-30
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| | * [IA64] fail mmaps that span areas with incompatible attributesBjorn Helgaas2007-03-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Example memory map (from HP sx1000 with VGA enabled): 0x00000 - 0x9FFFF supports only WB (cacheable) access 0xA0000 - 0xBFFFF supports only UC (uncacheable) access 0xC0000 - 0xFFFFF supports only WB (cacheable) access Some versions of X map the entire 0x00000-0xFFFFF area at once. With the example above, this mmap must fail because there's no memory attribute that's safe for the entire area. Prior to this patch, we performed the mmap with a UC mapping. When X accessed the WB memory at 0xC0000, it caused an MCA. The crash can happen when mapping 0xC0000 from either /dev/mem or a /sys/.../legacy_mem file. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * [IA64] allow WB /sys/.../legacy_mem mmapsBjorn Helgaas2007-03-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow cacheable mmaps of legacy_mem if WB access is supported for the region. The "legacy_mem" file often contains a shadow option ROM, and some versions of X depend on this. Tim Yamin <plasm@roo.me.uk> reported that this change fixes X on a Dell PowerEdge 3250. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * [IA64] make ioremap avoid unsupported attributesBjorn Helgaas2007-03-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Example memory map (from HP sx1000 with VGA enabled): 0x00000 - 0x9FFFF supports only WB (cacheable) access 0xA0000 - 0xBFFFF supports only UC (uncacheable) access 0xC0000 - 0xFFFFF supports only WB (cacheable) access pci_read_rom() indirectly uses ioremap(0xC0000) to read the shadow VGA option ROM. ioremap() used to default to a 16MB or 64MB UC kernel identity mapping, which would cause an MCA when reading 0xC0000 since only WB is supported there. X uses reads the option ROM to initialize devices. A smaller test case is: # echo 1 > /sys/bus/pci/devices/0000:aa:03.0/rom # cp /sys/bus/pci/devices/0000:aa:03.0/rom x To avoid this, we can use the same ioremap_page_range() strategy that most architectures use for all ioremaps. These page table mappings come out of the vmalloc area. On ia64, these are in region 5 (0xA... addresses) and typically use 16KB or 64KB mappings instead of 16MB or 64MB mappings. The smaller mappings give more flexibility to use the correct attributes. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * [IA64] rename ioremap variables to match i386Bjorn Helgaas2007-03-30
| | | | | | | | | | | | | | | | | | | | | No functional change, just use the same names as i386. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * | Pull percpu-dtc into release branchTony Luck2007-04-30
| |\ \
| | * | [IA64] relax per-cpu TLB requirement to DTCChen, Kenneth W2007-02-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of pinning per-cpu TLB into a DTR, use DTC. This will free up one TLB entry for application, or even kernel if access pattern to per-cpu data area has high temporal locality. Since per-cpu is mapped at the top of region 7 address, we just need to add special case in alt_dtlb_miss. The physical address of per-cpu data is already conveniently stored in IA64_KR(PER_CPU_DATA). Latency for alt_dtlb_miss is not affected as we can hide all the latency. It was measured that alt_dtlb_miss handler has 23 cycles latency before and after the patch. The performance effect is massive for applications that put lots of tlb pressure on CPU. Workload environment like database online transaction processing or application uses tera-byte of memory would benefit the most. Measurement with industry standard database benchmark shown an upward of 1.6% gain. While smaller workloads like cpu, java also showing small improvement. Signed-off-by: Ken Chen <kenneth.w.chen@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | [IA64] remove per-cpu ia64_phys_stacked_size_p8Chen, Kenneth W2007-02-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's not efficient to use a per-cpu variable just to store how many physical stack register a cpu has. Ever since the incarnation of ia64 up till upcoming Montecito processor, that variable has "glued" to 96. Having a variable in memory means that the kernel is burning an extra cacheline access on every syscall and kernel exit path. Such "static" value is better served with the instruction patching utility exists today. Convert ia64_phys_stacked_size_p8 into dynamic insn patching. This also has a pleasant side effect of eliminating access to per-cpu area while psr.ic=0 in the kernel exit path. (fixable for per-cpu DTC work, but why bother?) There are some concerns with the default value that the instruc- tion encoded in the kernel image. It shouldn't be concerned. The reasons are: (1) cpu_init() is called at CPU initialization. In there, we find out physical stack register size from PAL and patch two instructions in kernel exit code. The code in question can not be executed before the patching is done. (2) current implementation stores zero in ia64_phys_stacked_size_p8, and that's what the current kernel exit path loads the value with. With the new code, it is equivalent that we store reg size 96 in ia64_phys_stacked_size_p8, thus creating a better safety net. Given (1) above can never fail, having (2) is just a bonus. All in all, this patch allow one less memory reference in the kernel exit path, thus reducing syscall and interrupt return latency; and avoid polluting potential useful data in the CPU cache. Signed-off-by: Ken Chen <kenneth.w.chen@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * | | Pull error-inject into release branchTony Luck2007-04-30
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| | * | | [IA64] Itanium MC Error Injection Tool: Makefile changesFenghua Yu2007-01-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch has Makefile changes. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | [IA64] Itanium MC Error Injection Tool: Driver sysfs interfaceFenghua Yu2007-01-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This kernel driver patch provides sysfs interface for user application to call pal_mc_error_inject() procedure. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | [IA64] Itanium MC Error Injection Tool: Kernel configurationFenghua Yu2007-01-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch has kenrel configuration changes for the MC Error Injection Tool. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* | | | | Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6Linus Torvalds2007-05-07
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6: [SERIAL] sunsu: Fix section mismatch warnings. [SPARC64]: pgtable_cache_init() should be __init. [SPARC64]: Fix section mismatch warnings in arch/sparc64/kernel/prom.c [SPARC64]: Fix section mismatch warnings in arch/sparc64/kernel/pci.c [SPARC64]: Fix section mismatch warnings in arch/sparc64/kernel/console.c [MM]: sparse_init() should be __init. [SPARC64]: Update defconfig. [VIDEO]: Add Sun XVR-2500 framebuffer driver. [VIDEO]: Add Sun XVR-500 framebuffer driver. [SPARC64]: SUN4U PCI-E controller support. [SPARC]: Fix comment typo in smp4m_blackbox_current(). [SCSI] SUNESP: sun_esp.c needs linux/delay.h Fix up conflict in arch/sparc64/mm/init.c manually due to removal of pgtable_cache_init() through the -mm patches (even though that patch was also by David ;) Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| * | | | | [SPARC64]: pgtable_cache_init() should be __init.David S. Miller2007-05-07
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | [SPARC64]: Fix section mismatch warnings in arch/sparc64/kernel/prom.cDavid S. Miller2007-05-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IRQ translation init routines should all be __init. Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | [SPARC64]: Fix section mismatch warnings in arch/sparc64/kernel/pci.cDavid S. Miller2007-05-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | apb_calc_first_last(), apb_fake_ranges(), pci_of_scan_bus(), of_scan_pci_bridge(), pci_of_scan_bus(), and pci_scan_one_pbm() should all be __devinit. Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | [SPARC64]: Fix section mismatch warnings in arch/sparc64/kernel/console.cDavid S. Miller2007-05-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | probe_other_fhcs() and central_probe() should be __init Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | [SPARC64]: Update defconfig.David S. Miller2007-05-07
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | [SPARC64]: SUN4U PCI-E controller support.David S. Miller2007-05-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | | | [SPARC]: Fix comment typo in smp4m_blackbox_current().David S. Miller2007-05-07
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* | | | | | Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6Linus Torvalds2007-05-07
|\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6: (38 commits) sh: R7785RP board updates. sh: Update r7780rp defconfig. sh: Add die chain notifiers. sh: Fix APM emulation on hp6xx. sh: Wire up more IRQs for SH7709. sh: Solution Engine 7722 board support. sh: Fix r7780rp build. sh: kdump support. sh: Move clock reporting to its own proc entry. sh: Solution Engine SH7705 board and CPU updates. serial: sh-sci: Fix module clock refcount for serial console. serial: sh-sci: Fix module clock refcounting. sh: SH7722 clock framework support. sh: hp6xx pata_platform support. sh: Obey CONFIG_HZ for HZ definition. sh: Fix fstatat64() syscall. sh: se7780 PCI support. sh: SH7780 Solution Engine board support. sh: Add a dummy SH-4 PCIC fixup. sh: Tidy up L-BOX area5 addresses. ...
| * | | | | | sh: R7785RP board updates.Ryusuke Sakato2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some fixups for the R7785RP board. Gets iVDR working. Signed-off-by: Ryusuke Sakato <sakato.ryusuke@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: Update r7780rp defconfig.Paul Mundt2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: Add die chain notifiers.Paul Mundt2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the atomic die chains in, kprobes needs these. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: Fix APM emulation on hp6xx.Kristoffer Ericson2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the shared APM emulation code being introduced, hp6xx was missed in the conversion. Get it building again. Signed-off-by: Kristoffer Ericson <kristoffer.ericson@gmail.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: Wire up more IRQs for SH7709.Takashi YOSHII2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hp6xx requires some additional IRQs that aren't currently enabled in the SH7709 setup code. Wire them up. Signed-off-by: Takashi YOSHII <takashi.yoshii.ze@hitachi.com> Signed-off-by: Kristoffer Ericson <kristoffer.ericson@gmail.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: Solution Engine 7722 board support.Ryusuke Sakato2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds more full-featured support for the SH7722 Solution Engine. Previously this was using the generic board, and lacked most of the peripheral support. Signed-off-by: Ryusuke Sakato <sakato.ryusuke@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: kdump support.Paul Mundt2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for kexec based crash dumps. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: Move clock reporting to its own proc entry.Paul Mundt2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously this was done in cpuinfo, but with the number of clocks growing, it makes more sense to place this in a different proc entry. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: Solution Engine SH7705 board and CPU updates.Nobuhiro Iwamatsu2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes up SH7705 CPU support and the SE7705 board for some of the recent changes. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.zh@hitachi.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: SH7722 clock framework support.dmitry pervushin2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the SH7722 (MobileR) to the clock framework. Signed-off-by: dmitry pervushin <dimka@nomadgs.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: hp6xx pata_platform support.Kristoffer Ericson2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Drop the hd64461 I/O ops and wire up pata_platform for MMIO. Signed-off-by: Kristoffer Ericson <Kristoffer_e1@hotmail.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: se7780 PCI support.Nobuhiro Iwamatsu2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the SH7780 PCIC on the Solution Engine 7780, missing from the previous board-support patch. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.zh@hitachi.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: SH7780 Solution Engine board support.Nobuhiro Iwamatsu2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the SH7780-based Solution Engine reference board. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.zh@hitachi.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: Add a dummy SH-4 PCIC fixup.Paul Mundt2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default we don't have anything to fix up for the SH-4 PCIC, boards can overload this as necessary. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: Tidy up L-BOX area5 addresses.Paul Mundt2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | L-BOX can use the normal PA_AREA5_IO, there's no reason for it to reproduce it. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: Add defconfig for se7722.Paul Mundt2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: Kill off udivdi3 div64_32 wrapping.Paul Mundt2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we've been handling udivdi3 references and wrapping them in to div64_32() automatically. This doesn't get a lot of use, however, and as akpm noted in the recent thread on l-k: http://lkml.org/lkml/2007/2/27/241 we're better off simply ripping it out and going the do_div() route if there happen to be any places that need it. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: bootmem tidying for discontig/sparsemem preparation.Paul Mundt2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reworks some of the node 0 bootmem initialization in preparation for discontigmem and sparsemem support. ARCH_POPULATES_NODE_MAP is switched to as a result of this. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: Add defconfig for se7712.Nobuhiro Iwamatsu2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.zh@hitachi.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: MS7712SE01 board support.Nobuhiro Iwamatsu2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support the SH7712 (SH3-DSP) Solution Engine reference board. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: L-BOX RE2 support.Nobuhiro Iwamatsu2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the L-BOX RE2 router. http://www.nttcom.co.jp/l-box/ L-BOX RE2 is a SH7751R-based router. It has CF, Cardbus, serial, and LAN x2. This is one of the very few SH boards that a general person can obtain now. The L-BOX shipped with a 2.4.28 kernel, this is a rewritten patch adding it to current git. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: landisk updates.kogiidena2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updates for the landisk board: - The push_switch framework was used. - landisk_pwb.c was divided into psw.c and gio.c. - pata_platform was supported in USL-5P. - irq.c was rewritten. - io.c was replaced with generic I/O routines. Signed-off-by: kogiidena <kogiidena@eggplant.ddo.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: heartbeat double 0 fix.Takashi YOSHII2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This implements stricter and more compliant knightrider strobing in the heartbeat handler. While there still seems to be some debate as to whether the double 0 is "more" correct or not, this updated version appears to have general consensus. Fixes a long-term "bug". Signed-off-by: Takashi YOSHII <takashi.yoshii.ze@hitachi.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: pata_platform pcmcia support for SolutionEngine boards.Nobuhiro Iwamatsu2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables pata_platform support for the PCMCIA slot on the SolutionEngine. Signed-off-by: Nobuhiro Iwamatsu <hemamu@t-base.ne.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: Add SH7785 Highlander board support (R7785RP).Paul Mundt2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds preliminary support for the SH7785-based Highlander board. Some of the Highlander support code is reordered so that most of it can be reused directly. This also plugs in missing SH7785 checks in the places that need it, as this is the first board to support the CPU. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: NR_IRQS consolidation.Paul Mundt2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each board sets the total number of IRQs that it's interested in via the machvec. Previously we cared about the off vs on-chip IRQ range, but any code relying on that is long dead. Set NR_IRQS to something sensible given the vector range, and allow boards to cap it if they really care. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: generic BUG() support.Paul Mundt2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wire up GENERIC_BUG for SH. This moves off of the special bug frame and on to the generic struct bug_entry. Roughly the same semantics are retained, and we can kill off some of the verbose BUG() reporting code. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | | | | sh: speculative execution support for SH7780.Paul Mundt2007-05-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SH7780 has a speculative execution mode where it can speculatively perform an instruction fetch for subroutine returns, this allows it to be enabled. There are some various pitfalls associated with this mode, so it's left as depending on CONFIG_EXPERIMENTAL and not enabled by default. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 05:16:32 -0500