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* [MIPS] unexport copy_to_user_page()Dmitri Vorobiev2008-04-28
| | | | | | | | | The copy_to_user_page() function is called only in the core kernel code. Therefore, there is no need to export it. This patch removes EXPORT_SYMBOL(copy_to_user_page). Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] unexport copy_user_highpage()Dmitri Vorobiev2008-04-28
| | | | | | | | | The copy_user_highpage() routine has no users outside of the core kernel code, so exporting this symbol is pointless. This patch removes EXPORT_SYMBOL(copy_user_highpage). Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: move UART platform code to its proper placeSergei Shtylyov2008-04-28
| | | | | | | | | Move the code registering the Alchemy UART platform devices from drivers/serial/ to its proper place, into the Alchemy platform code. Fix the related Kconfig entry, while at it... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: kill useless #include's, #define's and extern'sSergei Shtylyov2008-04-28
| | | | | | | | Go thru the Alchemy code and hunt down every unneeded #include, #define, and extern (some of which refer to already long dead functions). Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] malta_int.c: make 4 variables staticDmitri Vorobiev2008-04-28
| | | | | | | | | | | | | | | The following variables defined in arch/mips/mips-boards/malta/malta_int.c can become static: msc_irqmap[], msc_nr_irqs, msc_eicirqmap[], and msc_nr_eicirqs. This patch makes them static. Successfully build-tested using default configs for Malta, Atlas and SEAD boards. Runtime test successfully performed by booting the Malta 4Kc board up to the shell prompt. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] make standard_io_resources[] staticDmitri Vorobiev2008-04-28
| | | | | | | | | | | | | | The array standard_io_resources[] needs not to be exposed in the kernel global namespace. This patch makes it static. Successfully build-tested using default configs for Malta, Atlas and SEAD boards. Runtime test successfully performed by booting the Malta 4Kc board up to the shell prompt. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] make plat_perf_setup() staticDmitri Vorobiev2008-04-28
| | | | | | | | | | | | | | There is no need for the plat_perf_setup() function to be global, so make it static. Successfully build-tested using default configs for Malta, Atlas and SEAD boards. Runtime test successfully performed by booting the Malta 4Kc board up to the shell prompt. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] make mdesc and prom_getmdesc() staticDmitri Vorobiev2008-04-28
| | | | | | | | | | | | | | Neither the mdesc[] array nor the prom_getmdesc() function need to be global. This patch makes them static. Successfully build-tested using default configs for Malta, Atlas and SEAD boards. Runtime test successfully performed by booting the Malta 4Kc board up to the shell prompt. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] make mips_ejtag_setup() staticDmitri Vorobiev2008-04-28
| | | | | | | | | | | | | This change makes the needlessly global function mips_ejtag_setup() static. Successfully build-tested using default configs for Malta, Atlas and SEAD boards. Runtime test successfully performed by booting the Malta 4Kc board up to the shell prompt. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] make mips_nmi_setup() staticDmitri Vorobiev2008-04-28
| | | | | | | | | | | | | This change makes the needlessly global function mips_nmi_setup() static. Successfully build-tested using default configs for Malta, Atlas and SEAD boards. Runtime test successfully performed by booting the Malta 4Kc board up to the shell prompt. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] replace remaining __FUNCTION__ occurrencesHarvey Harrison2008-04-28
| | | | | | | | __FUNCTION__ is gcc-specific, use __func__ Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] remove redundant display of free swap space in show_mem()Johannes Weiner2008-04-28
| | | | | | Signed-off-by: Johannes Weiner <hannes@saeurebad.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: kill useless time variablesSergei Shtylyov2008-04-28
| | | | | | | | | | | | Since the commit 91a2fcc88634663e9e13dcdfad0e4a860e64aeee ([MIPS] Consolidate all variants of MIPS cp0 timer interrupt handlers) removed the Alchemy specific timer handler, 'r4k_offset' and 'r4k_cur' variables became practically useless, so get rid of them at last, renaming cal_r4off() function into calc_clock() and making it return CPU frequency. Also, make 'no_au1xxx_32khz' variable static... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: don't unmask timer IRQ earlySergei Shtylyov2008-04-28
| | | | | | | | | | | | | | | | | | Defer the unmasking of the count/compare interrupt (IRQ5) till the clockevent driver initialization: - only enable the cascaded IRQs 0 thru 4 in arch_init_irq(); kill the ALLINTS macro -- this change is blessed by AMD as I saw it in their own patch; :-) - do not force IRQ5 enabled in plat_time_init() if PM is enabled and there's no 32 KHz crystal. Update the copyrights (taking into account my prior changes), also removing Pete Popov's old email... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Move arch/mips/philips to arch/mips/nxpDaniel Laird2008-04-28
| | | | | Signed-off-by: daniel.j.laird <daniel.j.laird@nxp.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] replace __inline with inlineHarvey Harrison2008-04-28
| | | | | Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add support for MIPS CMP platform.Ralf Baechle2008-04-28
| | | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add CoreFPGA5 support; distinguish between SOCit/ROCitChris Dearman2008-04-28
| | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add noulri kernel argument to disable "rdhwr $29" usermode support.Chris Dearman2008-04-28
| | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Allow setting of the cache attribute at run time.Chris Dearman2008-04-28
| | | | | | | | Slightly tacky, but there is a precedent in the sparc archirecture code. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] All MIPS32 processors support64-bit physical addresses.Chris Dearman2008-04-28
| | | | | | | Still, only the 4K may actually implement it. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Remove TLB sanitation codeChris Dearman2008-04-28
| | | | | | | It is not being used by Malta and shouldn't be needed for MIPSsim. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Basic SPRAM supportChris Dearman2008-04-28
| | | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Reimplement clear_page/copy_pageThiemo Seufer2008-04-28
| | | | | | | | | | | | | | | | | Fold the SB-1 specific implementation of clear_page/copy_page in the generic version, and rewrite that one in tlbex style. The immediate benefits: - It converts the compile-time workaround for SB-1 pass 1 prefetches to a more efficient run-time check. - It allows adjustment of loop unfolling, which helps to reduce the number of redundant cdex cache ops. - It fixes some esoteric cornercases (the cache line length calculations can go wrong, and support for 64k pages without prefetch instructions will overflow the addiu immediate). - Somewhat better guesses of "good" prefetch values. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'kvm-updates-2.6.26' of ↵Linus Torvalds2008-04-27
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/avi/kvm * 'kvm-updates-2.6.26' of git://git.kernel.org/pub/scm/linux/kernel/git/avi/kvm: (147 commits) KVM: kill file->f_count abuse in kvm KVM: MMU: kvm_pv_mmu_op should not take mmap_sem KVM: SVM: remove selective CR0 comment KVM: SVM: remove now obsolete FIXME comment KVM: SVM: disable CR8 intercept when tpr is not masking interrupts KVM: SVM: sync V_TPR with LAPIC.TPR if CR8 write intercept is disabled KVM: export kvm_lapic_set_tpr() to modules KVM: SVM: sync TPR value to V_TPR field in the VMCB KVM: ppc: PowerPC 440 KVM implementation KVM: Add MAINTAINERS entry for PowerPC KVM KVM: ppc: Add DCR access information to struct kvm_run ppc: Export tlb_44x_hwater for KVM KVM: Rename debugfs_dir to kvm_debugfs_dir KVM: x86 emulator: fix lea to really get the effective address KVM: x86 emulator: fix smsw and lmsw with a memory operand KVM: x86 emulator: initialize src.val and dst.val for register operands KVM: SVM: force a new asid when initializing the vmcb KVM: fix kvm_vcpu_kick vs __vcpu_run race KVM: add ioctls to save/store mpstate KVM: Rename VCPU_MP_STATE_* to KVM_MP_STATE_* ...
| * KVM: MMU: kvm_pv_mmu_op should not take mmap_semMarcelo Tosatti2008-04-27
| | | | | | | | | | | | | | | | | | | | | | kvm_pv_mmu_op should not take mmap_sem. All gfn_to_page() callers down in the MMU processing will take it if necessary, so as it is it can deadlock. Apparently a leftover from the days before slots_lock. Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: SVM: remove selective CR0 commentJoerg Roedel2008-04-27
| | | | | | | | | | | | | | | | | | | | | | There is not selective cr0 intercept bug. The code in the comment sets the CR0.PG bit. But KVM sets the CR4.PG bit for SVM always to implement the paged real mode. So the 'mov %eax,%cr0' instruction does not change the CR0.PG bit. Selective CR0 intercepts only occur when a bit is actually changed. So its the right behavior that there is no intercept on this instruction. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: SVM: remove now obsolete FIXME commentJoerg Roedel2008-04-27
| | | | | | | | | | | | | | With the usage of the V_TPR field this comment is now obsolete. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: SVM: disable CR8 intercept when tpr is not masking interruptsJoerg Roedel2008-04-27
| | | | | | | | | | | | | | | | | | This patch disables the intercept of CR8 writes if the TPR is not masking interrupts. This reduces the total number CR8 intercepts to below 1 percent of what we have without this patch using Windows 64 bit guests. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: SVM: sync V_TPR with LAPIC.TPR if CR8 write intercept is disabledJoerg Roedel2008-04-27
| | | | | | | | | | | | | | | | If the CR8 write intercept is disabled the V_TPR field of the VMCB needs to be synced with the TPR field in the local apic. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: export kvm_lapic_set_tpr() to modulesJoerg Roedel2008-04-27
| | | | | | | | | | | | | | | | This patch exports the kvm_lapic_set_tpr() function from the lapic code to modules. It is required in the kvm-amd module to optimize CR8 intercepts. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: SVM: sync TPR value to V_TPR field in the VMCBJoerg Roedel2008-04-27
| | | | | | | | | | | | | | | | This patch adds syncing of the lapic.tpr field to the V_TPR field of the VMCB. With this change we can safely remove the CR8 read intercept. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: ppc: PowerPC 440 KVM implementationHollis Blanchard2008-04-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This functionality is definitely experimental, but is capable of running unmodified PowerPC 440 Linux kernels as guests on a PowerPC 440 host. (Only tested with 440EP "Bamboo" guests so far, but with appropriate userspace support other SoC/board combinations should work.) See Documentation/powerpc/kvm_440.txt for technical details. [stephen: build fix] Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com> Acked-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: x86 emulator: fix lea to really get the effective addressAvi Kivity2008-04-27
| | | | | | | | | | | | We never hit this, since there is currently no reason to emulate lea. Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: x86 emulator: fix smsw and lmsw with a memory operandAvi Kivity2008-04-27
| | | | | | | | | | | | | | | | lmsw and smsw were implemented only with a register operand. Extend them to support a memory operand as well. Fixes Windows running some display compatibility test on AMD hosts. Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: x86 emulator: initialize src.val and dst.val for register operandsAvi Kivity2008-04-27
| | | | | | | | | | | | This lets us treat the case where mod == 3 in the same manner as other cases. Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: SVM: force a new asid when initializing the vmcbAvi Kivity2008-04-27
| | | | | | | | | | | | | | Shutdown interception clears the vmcb, leaving the asid at zero (which is illegal. so force a new asid on vmcb initialization. Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: fix kvm_vcpu_kick vs __vcpu_run raceMarcelo Tosatti2008-04-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a window open between testing of pending IRQ's and assignment of guest_mode in __vcpu_run. Injection of IRQ's can race with __vcpu_run as follows: CPU0 CPU1 kvm_x86_ops->run() vcpu->guest_mode = 0 SET_IRQ_LINE ioctl .. kvm_x86_ops->inject_pending_irq kvm_cpu_has_interrupt() apic_test_and_set_irr() kvm_vcpu_kick if (vcpu->guest_mode) send_ipi() vcpu->guest_mode = 1 So move guest_mode=1 assignment before ->inject_pending_irq, and make sure that it won't reorder after it. Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: add ioctls to save/store mpstateMarcelo Tosatti2008-04-27
| | | | | | | | | | | | | | | | | | | | | | | | | | So userspace can save/restore the mpstate during migration. [avi: export the #define constants describing the value] [christian: add s390 stubs] [avi: ditto for ia64] Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Carsten Otte <cotte@de.ibm.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: Rename VCPU_MP_STATE_* to KVM_MP_STATE_*Avi Kivity2008-04-27
| | | | | | | | | | | | We wish to export it to userspace, so move it into the kvm namespace. Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: hlt emulation should take in-kernel APIC/PIT timers into accountMarcelo Tosatti2008-04-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Timers that fire between guest hlt and vcpu_block's add_wait_queue() are ignored, possibly resulting in hangs. Also make sure that atomic_inc and waitqueue_active tests happen in the specified order, otherwise the following race is open: CPU0 CPU1 if (waitqueue_active(wq)) add_wait_queue() if (!atomic_read(pit_timer->pending)) schedule() atomic_inc(pit_timer->pending) Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: SVM: do not intercept task switch with NPTJoerg Roedel2008-04-27
| | | | | | | | | | | | | | | | When KVM uses NPT there is no reason to intercept task switches. This patch removes the intercept for it in that case. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: Add kvm trace userspace interfaceFeng(Eric) Liu2008-04-27
| | | | | | | | | | | | | | | | This interface allows user a space application to read the trace of kvm related events through relayfs. Signed-off-by: Feng (Eric) Liu <eric.e.liu@intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: ia64: Stub out kvmtraceAvi Kivity2008-04-27
| | | | | | | | Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: s390: Stub out kvmtraceAvi Kivity2008-04-27
| | | | | | | | Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: Add trace markersFeng (Eric) Liu2008-04-27
| | | | | | | | | | | | | | | | Trace markers allow userspace to trace execution of a virtual machine in order to monitor its performance. Signed-off-by: Feng (Eric) Liu <eric.e.liu@intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: SVM: add intercept for machine check exceptionJoerg Roedel2008-04-27
| | | | | | | | | | | | | | | | | | To properly forward a MCE occured while the guest is running to the host, we have to intercept this exception and call the host handler by hand. This is implemented by this patch. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: SVM: align shadow CR4.MCE with hostJoerg Roedel2008-04-27
| | | | | | | | | | | | | | | | This patch aligns the host version of the CR4.MCE bit with the CR4 active in the guest. This is necessary to get MCE exceptions when the guest is running. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: SVM: indent svm_set_cr4 with tabs instead of spacesJoerg Roedel2008-04-27
| | | | | | | | | | | | | | | | The svm_set_cr4 function is indented with spaces. This patch replaces them with tabs. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
| * KVM: MMU: Don't assume struct page for x86Anthony Liguori2008-04-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a gfn_to_pfn() function and corresponding functions like kvm_release_pfn_dirty(). Using these new functions, we can modify the x86 MMU to no longer assume that it can always get a struct page for any given gfn. We don't want to eliminate gfn_to_page() entirely because a number of places assume they can do gfn_to_page() and then kmap() the results. When we support IO memory, gfn_to_page() will fail for IO pages although gfn_to_pfn() will succeed. This does not implement support for avoiding reference counting for reserved RAM or for IO memory. However, it should make those things pretty straight forward. Since we're only introducing new common symbols, I don't think it will break the non-x86 architectures but I haven't tested those. I've tested Intel, AMD, NPT, and hugetlbfs with Windows and Linux guests. [avi: fix overflow when shifting left pfns by adding casts] Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
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