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* [PATCH] sparsemem extreme implementationBob Picco2005-09-05
| | | | | | | | | | | | | | | | | | | | | | | | With cleanups from Dave Hansen <haveblue@us.ibm.com> SPARSEMEM_EXTREME makes mem_section a one dimensional array of pointers to mem_sections. This two level layout scheme is able to achieve smaller memory requirements for SPARSEMEM with the tradeoff of an additional shift and load when fetching the memory section. The current SPARSEMEM implementation is a one dimensional array of mem_sections which is the default SPARSEMEM configuration. The patch attempts isolates the implementation details of the physical layout of the sparsemem section array. SPARSEMEM_EXTREME requires bootmem to be functioning at the time of memory_present() calls. This is not always feasible, so architectures which do not need it may allocate everything statically by using SPARSEMEM_STATIC. Signed-off-by: Andy Whitcroft <apw@shadowen.org> Signed-off-by: Bob Picco <bob.picco@hp.com> Signed-off-by: Dave Hansen <haveblue@us.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] SPARSEMEM EXTREMEBob Picco2005-09-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | A new option for SPARSEMEM is ARCH_SPARSEMEM_EXTREME. Architecture platforms with a very sparse physical address space would likely want to select this option. For those architecture platforms that don't select the option, the code generated is equivalent to SPARSEMEM currently in -mm. I'll be posting a patch on ia64 ml which uses this new SPARSEMEM feature. ARCH_SPARSEMEM_EXTREME makes mem_section a one dimensional array of pointers to mem_sections. This two level layout scheme is able to achieve smaller memory requirements for SPARSEMEM with the tradeoff of an additional shift and load when fetching the memory section. The current SPARSEMEM -mm implementation is a one dimensional array of mem_sections which is the default SPARSEMEM configuration. The patch attempts isolates the implementation details of the physical layout of the sparsemem section array. ARCH_SPARSEMEM_EXTREME depends on 64BIT and is by default boolean false. I've boot tested under aim load ia64 configured for ARCH_SPARSEMEM_EXTREME. I've also boot tested a 4 way Opteron machine with !ARCH_SPARSEMEM_EXTREME and tested with aim. Signed-off-by: Andy Whitcroft <apw@shadowen.org> Signed-off-by: Bob Picco <bob.picco@hp.com> Signed-off-by: Dave Hansen <haveblue@us.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] v850: Add show_memMiles Bader2005-09-02
| | | | | Signed-off-by: Miles Bader <miles@gnu.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] v850: Update defconfigsMiles Bader2005-09-02
| | | | | Signed-off-by: Miles Bader <miles@gnu.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] v850: Round up length passed to slram driver to a multiple of ↵Miles Bader2005-09-02
| | | | | | | SLRAM_BLK_SZ Signed-off-by: Miles Bader <miles@gnu.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] m68knommu: update defconfig for m68knommuGreg Ungerer2005-09-02
| | | | | | | | Updated defconfig for m68knommu arch. Patch originaly submitted by Jan Dittmer <jdittmer@ppp0.net> Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] m68knommu: new board support in linker scriptGreg Ungerer2005-09-02
| | | | | | | | | | . add support for the M5235EVB board . add support for the SOM5282 board . add support for the MOD5272 board . fix end of memory define for eLITE board Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] m68knommu: use THREAD_SIZE instead of hard coded sizeGreg Ungerer2005-09-02
| | | | | | | | Use the THREAD_SIZE define when manipulating the stack instead of hard coded values (for the 68328 and 68360 sub-architectures). Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] m68knommu: new family (523x) and board config supportGreg Ungerer2005-09-02
| | | | | | | | | | | | | New architecture and board configuration support for m68knommu. . add 523x ColdFire support . add support for SOM5282 and MOD5272 boards . break up the 527x to be separate 5271 and 5275. There is some subtle differences that (like RAM config) that need to be dealt with . add option to support selecting 4k kernel stack Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] m68knommu: 523x ColdFire processor support in arch MakefileGreg Ungerer2005-09-02
| | | | | | | Add support for the 523x ColdFire family of processors Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] m68knommu: cleanup showstack()Greg Ungerer2005-09-02
| | | | | | | | | Make show_stack() consistent with other architectures. Put the vector string names in the .rodata section. Patch originally submitted by Philippe De Muyter <phdm@macqel.be>. Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] m68knommu: fix ColdFire startup code to properly handle non 0 based ramGreg Ungerer2005-09-02
| | | | | | | | | Correctly determine the end of ram for ram setups that do not start at base address of 0. Add support for the MOD5272 board, which doesn not have a ram base of 0. Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] m68knommu: new family (523x) and board setupGreg Ungerer2005-09-02
| | | | | | | | | . setup for the new 523x ColdFire family . break up of 527x to be 5271 and 5275 . some white space cleanup Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] m68knommu: 523x ColdFire processor init codeGreg Ungerer2005-09-02
| | | | | | | Low level initialization code for the 523x ColdFire processor family. Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Merge HEAD from master.kernel.org:/home/rmk/linux-2.6-arm Linus Torvalds2005-09-02
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| * [ARM] Fix ARMv6 page table bitsRussell King2005-09-01
| | | | | | | | | | | | | | | | We weren't explicitly setting the page table bits we desired in user_prot in the protection table, which resulted in the user mappings for v6 CPUs being marked global. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] Simplify setup_mm_for_reboot()Russell King2005-09-01
| | | | | | | | | | | | | | | | No point checking what CPU architecture level we have each time within the loop, so precompute the base PMD flags outside the loop. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] Convert open-coded __pmd_populate to use inline functionRussell King2005-09-01
| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] 2864/1: VST aka CONFIG_NO_IDLE_HZ support for SA11x0Nicolas Pitre2005-09-01
| | | | | | | | | | | | | | Patch from Nicolas Pitre Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] 2863/1: clarify comment in PXA2xx and SA1x00 timer codeNicolas Pitre2005-09-01
| | | | | | | | | | | | | | Patch from Nicolas Pitre Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] 2862/1: VST aka CONFIG_NO_IDLE_HZ support for PXA2xxNicolas Pitre2005-09-01
| | | | | | | | | | | | | | Patch from Nicolas Pitre Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] 2865/2: fix fadvise64_64 syscall argument passingNicolas Pitre2005-09-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Nicolas Pitre The prototype for sys_fadvise64_64() is: long sys_fadvise64_64(int fd, loff_t offset, loff_t len, int advice) The argument list is therefore as follows on legacy ABI: fd: type int (r0) offset: type long long (r1-r2) len: type long long (r3-sp[0]) advice: type int (sp[4]) With EABI this becomes: fd: type int (r0) offset: type long long (r2-r3) len: type long long (sp[0]-sp[4]) advice: type int (sp[8]) Not only do we have ABI differences here, but the EABI version requires one additional word on the syscall stack. To avoid the ABI mismatch and the extra stack space required with EABI this syscall is now defined with a different argument ordering on ARM as follows: long sys_arm_fadvise64_64(int fd, int advice, loff_t offset, loff_t len) This gives us the following ABI independent argument distribution: fd: type int (r0) advice: type int (r1) offset: type long long (r2-r3) len: type long long (sp[0]-sp[4]) Now, since the syscall entry code takes care of 5 registers only by default including the store of r4 to the stack, we need a wrapper to store r5 to the stack as well. Because that wrapper was missing and was always required this means that sys_fadvise64_64 never worked on ARM and therefore we can safely reuse its syscall number for our new sys_arm_fadvise64_64 interface. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge refs/heads/release from ↵Linus Torvalds2005-09-01
|\ \ | | | | | | | | | master.kernel.org:/pub/scm/linux/kernel/git/aegl/linux-2.6
| * \ Auto-update from upstreamTony Luck2005-08-31
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| * | | [IA64] uncached allocator: use generic (not sn2 specific) functionsMartin Hicks2005-08-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change sn2-specific calls into generic functions. Without this change the uncached allocator will not work on non-sn2 platforms. Signed-off-by: Greg Edwards <edwardsg@sgi.com> Signed-off-by: Martin Hicks <mort@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * | | Auto-update from upstreamTony Luck2005-08-30
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| * \ \ \ Pull rationalise-regions into release branchTony Luck2005-08-29
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| | * | | | [IA64] Rationalise Region DefinitionsPeter Chubb2005-08-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, region numbers are defined in several files, with several names. For example, we have REGION_KERNEL in asm/page.h and RGN_KERNEL in pgtable.h We also have address definitions that should depend on the RGN_XXX macros, but are currently just long constants. The following patch reorganises all the definitions so that they have the same form (RGN_XXX), are in one place, and that addresses that depend on RGN_XXX are derived from them. (This is a necessary but not sufficient patch to allow UML-like operation on IA64). Thanks to David Mosberger for catching the change I missed in mmu_context.h. Signed-off-by: Peter Chubb <peterc@gelato.unsw.edu.au> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * | | | | Pull ngam-maule-steiner into release branchTony Luck2005-08-29
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| | * | | | | [IA64-SGI] fix bte_copy() calling smp_processor_id() while preemptibleRuss Anderson2005-08-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | bte_copy() calls calls smp_processor_id(), which will get flagged if preemption if enabled. raw_smp_processor_id() is used instead because we are just using it to pick a BTE interface and are not tied to a specific cpu. Signed-off-by: Russ Anderson (rja@sgi.com) Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | | [IA64] altix: Abstract irq_affinity at the sn pci providerMark Maule2005-08-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Altix patch to abstract irq_affinity down to the pci provider level since different SGI hardware implements this in different ways. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | | [IA64] SGI SN remove redundant partition SAL callRuss Anderson2005-08-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean up of SGI SN partitioning related code. The SN_SAL_GET_SN_INFO SAL call returns the partition ID, making the SN_SAL_SYSCTL_PARTITION_GET SAL call redundant. Remove sn_partid and use sn_partition_id. Signed-off-by: Russ Anderson (rja@sgi.com) Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | | [IA64] - SGI SN hwperf enhancements -Mark Goodwin2005-08-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the SN pci device info to use the nearest node function to allocate driver memory on the nearest node (rather than defaulting to node 0). Signed-off-by: Mark Goodwin <markgw@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | | [IA64] - SGI SN hwperf enhancements -Mark Goodwin2005-08-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new exported function for determining the nearest node with CPUs for I/O nodes and fix a bug where the hwperf dynamic misc device was being registered before misc_init(). Signed-off-by: Mark Goodwin <markgw@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | | [IA64] - SGI SN hwperf enhancements - export_pci_topologyMark Goodwin2005-08-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bugfix to export PCI topology information in /proc/sgi_sn/sn_topology. Signed-off-by: Mark Goodwin <markgw@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | | [IA64-SGI] - New SN hardware support - ptc_fixesJack Steiner2005-08-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Shub2 provides a much improved mechanism for issuing internode TLB purges. Add code to support the newer mechanism. There is also some debug code (disabled) that is useful for testing. Collect statistics on the number, type & duration of TLB purges. This data will be useful for making future improvements in the algorithms. Signed-off-by: Jack Steiner <steiner@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | | [IA64-SGI] - New SN hardware support - cpu_relaxJack Steiner2005-08-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a few missing calls to "hint @pause". Signed-off-by: Jack Steiner <steiner@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | | [IA64-SGI] - New SN hardware support - bte_fixesJack Steiner2005-08-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the BTE driver so that it works for both shub1 and shub2. Most of the changes are related to the number of cores that use the BTE engine, to the MMR addresses of various shub registers, and to using the correct processor or network physical address. Signed-off-by: Russ Anderson <rja@sgi.com> Signed-off-by: Jack Steiner <steiner@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | | [IA64-SGI] - New SN hardware support - no_warsJack Steiner2005-08-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disable some shub1-specific code when running on systems with shub2. Signed-off-by: Jack Steiner <steiner@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | | [IA64-SGI] - New SN hardware support - boot_init_shub2Jack Steiner2005-08-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the addresses of the pio_write_status_addr so that they are correct for newer processors. Shub2 did not number the threads in the order that I had expected. Signed-off-by: Jack Steiner <steiner@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | | [IA64-SGI] - New SN hardware support - use_alias_spaceJack Steiner2005-08-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use local SHUB alias space when referencing MMRs that are known to be node local. There is a slight performance benefit & code simplification. Signed-off-by: Jack Steiner <steiner@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | | [IA64-SGI] sn pci provider for TIOCE (pciMark Maule2005-08-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Altix patch to add an SN pci provider for TIOCE, which is SGI's PCI Express implementation. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | | [IA64-SGI] add support for TIO huge-windowMark Maule2005-08-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Altix patch to add TIO "huge-window" address support to sn_dma_flush(). Update copyright in affected files. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | | [IA64-SGI] abstract force_interrupt() mechanismMark Maule2005-08-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Altix patch to abstract the force_interrupt() mechanism away from the pcibr provider. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | | [IA64-SGI] altix: cosmetic rename of SGI_PCIBR_ERRORMark Maule2005-08-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cosmetic altix patch to rename SGI_PCIBR_ERROR to something more generic and remove a duplicate #define. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | | [IA64-SGI] Altix only: Add PCI Domain number support.Colin Ngam2005-08-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables PCI Domain numbering on Altix. Signed-off-by: Colin Ngam <cngam@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * | | | | | Pull pending-2.6.14 into release branchTony Luck2005-08-29
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| | * | | | | | [IA64] Delete erroneous copy_page.o in global lib-y listKenneth Chen2005-08-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | copy_page.o appeared twice in arch/ia64/lib/Makefile. The one in global lib-y is wrong where it should be just in lib-$(CONFIG_ITANIUM). Both copy_page.o and copy_page_mck.o are build for Itanium2 processor and the link order will pick up the low performing copy_page function (originally written for itanium processor). In this case, we really want the copy_page_mck.o for optimized version. Signed-off-by: Kenneth Chen <kenneth.w.chen@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | | | [IA64] arch/ia64/hp/sim/boot/fw-emu.c: remove egcs workaroundAdrian Bunk2005-08-24
| | | |/ / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kernel 2.6 doesn't support egcs, and I didn't find any user of this function. Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * | | | | | Pull acpi-p-state into release branchTony Luck2005-08-29
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