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* x86: Move PCI IO ECS code to x86/pciRobert Richter2008-07-08
| | | | | | | "Form follows function". Code is now where it belongs to. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86/pci: Renaming k8-bus_64.c to amd_bus.cRobert Richter2008-07-08
| | | | | | | The name fits better since this is code not only for K8. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: add C1E aware idle function, fixThomas Gleixner2008-07-08
| | | | | | | | | | | | | | | | | On Tue, 17 Jun 2008, Rafael J. Wysocki wrote: > > BTW, with the C1E patches reverted I don't get the > WARNING: at /home/rafael/src/linux-next/kernel/smp.c:215 smp_call_function_single+0x3d/0xa2 > in the log. Thomas? The BROADCAST_FORCE notification uses smp_function_call and therefor must be run with interrupts enabled. While at it, add a comment for the BROADCAST_EXIT notifier as well. Reported-and-bisected-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86, clockevents: add C1E aware idle functionThomas Gleixner2008-07-08
| | | | | | | | | | | | | | | | | | | | C1E on AMD machines is like C3 but without control from the OS. Up to now we disabled the local apic timer for those machines as it stops when the CPU goes into C1E. This excludes those machines from high resolution timers / dynamic ticks, which hurts especially X2 based laptops. The current boot time C1E detection has another, more serious flaw as well: some BIOSes do not enable C1E until the ACPI processor module is loaded. This causes systems to stop working after that point. To work nicely with C1E enabled machines we use a separate idle function, which checks on idle entry whether C1E was enabled in the Interrupt Pending Message MSR. This allows us to do timer broadcasting for C1E and covers the late enablement of C1E as well. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: move more common idle functions/variables to process.cThomas Gleixner2008-06-10
| | | | | | | more unification. Should cause no change in functionality. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: use cpuid to check MWAIT support for C1Thomas Gleixner2008-06-10
| | | | | | | | | | | cpuid(0x05) provides extended information about MWAIT in EDX when bit 0 of ECX is set. Bit 4-7 of EDX determine whether MWAIT is supported for C1. C1E enabled CPUs have these bits set to 0. Based on an earlier patch from Andi Kleen. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: use cpuinfo to check for interrupt pending message msrThomas Gleixner2008-06-10
| | | | | | | | Simplify code: no need to do a cpuid(1) again. The cpuinfo structure has all necessary information already. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: cleanup C1E enabled detectionThomas Gleixner2008-06-10
| | | | | | | | Rename the "MSR_K8_ENABLE_C1E" MSR to INT_PENDING_MSG, which is the name in the data sheet as well. Move the C1E mask to the header file. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: simplify idle selectionThomas Gleixner2008-06-10
| | | | | | | | | default_idle is selected in cpu_idle(), when no other idle routine is selected. Select it in select_idle_routine() when mwait is not selected. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* fix build bug in "x86: add PCI extended config space access for AMD Barcelona"Robert Richter2008-06-10
| | | | | | | Also much less code now. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: move bugs_64.c to cpu/bugs_64.cHiroshi Shimamoto2008-06-03
| | | | | | | It looks good to move bugs_64.c to cpu/bugs_64.c. Signed-off-by: Hiroshi Shimamoto <h-shimamoto@ct.jp.nec.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* fix build bug in "x86: add PCI extended config space access for AMD Barcelona"Ingo Molnar2008-06-02
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* x86: add PCI extended config space access for AMD BarcelonaRobert Richter2008-06-02
| | | | | | | | | | This patch implements PCI extended configuration space access for AMD's Barcelona CPUs. It extends the method using CF8/CFC IO addresses. An x86 capability bit has been introduced that is set for CPUs supporting PCI extended config space accesses. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: fix overlong line in arch/x86/kernel/cpu/amd_64.cH. Peter Anvin2008-05-30
| | | | | | Clean up an overlong line in arch/x86/kernel/cpu/amd_64.c. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* x86: Move the 64-bit Centaur specific parts out of setup_64.cDave Jones2008-05-30
| | | | | | | | Create a separate centaur_64.c file in the cpu/ dir for the useful parts to live in. Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* x86: Remove workaround for prescott (32bit P4) from 64-bit code.Dave Jones2008-05-30
| | | | | Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* x86: Move the 64-bit Intel specific parts out of setup_64.cDave Jones2008-05-30
| | | | | | | | Create a separate intel_64.c file in the cpu/ dir for the useful parts to live in. Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* x86: Move the AMD64 specific parts out of setup_64.cDave Jones2008-05-30
| | | | | | | | Create a separate amd_64.c file in the cpu/ dir for the useful parts to live in. Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* x86: move mmconfig declarations to headerThomas Gleixner2008-05-30
| | | | | | | | | arch/x86/kernel/mmconf-fam10h_64.c is missing the prototypes, which are decalred in arch/x86/kernel/setup_64.c. Move the prototypes and the inline stubs to the appropriate header file. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* Kconfig: introduce ARCH_DEFCONFIG to DEFCONFIG_LISTSam Ravnborg2008-05-25
| | | | | | | | | | | | | | | | | | init/Kconfig contains a list of configs that are searched for if 'make *config' are used with no .config present. Extend this list to look at the config identified by ARCH_DEFCONFIG. With this change we now try the defconfig targets last. This fixes a regression reported by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com>
* Merge branch 'x86-fixes-for-linus' of ↵Linus Torvalds2008-05-24
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux-2.6-tip * 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux-2.6-tip: x86: prevent PGE flush from interruption/preemption x86: use explicit copy in vdso_gettimeofday() namespacecheck: automated fixes x86/xen: fix arbitrary_virt_to_machine() x86: don't read maxlvt before checking if APIC is mapped x86: disable TSC for sched_clock() when calibration failed x86: distangle user disabled TSC from unstable x86: fix setup of cyc2ns in tsc_64.c
| * x86: use explicit copy in vdso_gettimeofday()Andi Kleen2008-05-23
| | | | | | | | | | | | | | | | | | | | | | | | Jeremy's gcc 3.4 seems to be unable to inline a 8 byte memcpy. But the vdso doesn't support external references. Copy the structure members of struct timezone explicitely instead. Signed-off-by: Andi Kleen <ak@linux.intel.com> Cc: Jeremy Fitzhardinge <jeremy@goop.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * namespacecheck: automated fixesIngo Molnar2008-05-23
| | | | | | | | Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86/xen: fix arbitrary_virt_to_machine()Jan Beulich2008-05-23
| | | | | | | | | | | | | | | | | | | | While I realize that the function isn't currently being used, I still think an obvious mistake like this should be corrected. Signed-off-by: Jan Beulich <jbeulich@novell.com> Acked-by: Jeremy Fitzhardinge <jeremy@goop.org> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * x86: don't read maxlvt before checking if APIC is mappedChuck Ebbert2008-05-23
| | | | | | | | | | | | | | | | | | | | A check for unmapped apic was added before reading maxlvt but the early read of maxlvt wasn't removed. Signed-off-by: Chuck Ebbert <cebbert@redhat.com> Cc: Andi Kleen <ak@suse.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: stable@kernel.org
| * x86: disable TSC for sched_clock() when calibration failedThomas Gleixner2008-05-23
| | | | | | | | | | | | | | | | When the TSC calibration fails then TSC is still used in sched_clock(). Disable it completely in that case. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: stable@kernel.org
| * x86: distangle user disabled TSC from unstableThomas Gleixner2008-05-23
| | | | | | | | | | | | | | | | | | | | | | tsc_enabled is set to 0 from the command line switch "notsc" and from the mark_tsc_unstable code. Seperate those functionalities and replace tsc_enable with tsc_disable. This makes also the native_sched_clock() decision when to use TSC understandable. Preparatory patch to solve the sched_clock() issue on 32 bit. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * x86: fix setup of cyc2ns in tsc_64.cThomas Gleixner2008-05-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the TSC is calibrated against the PIT due to the nonavailability of PMTIMER/HPET or due to SMI interference then the setup of the per CPU cyc2ns variables is skipped. This is unlikely to happen but it would definitely render sched_clock() unusable. This was introduced with commit 53d517cdbaac704352b3d0c10fecb99e0b54572e x86: scale cyc_2_nsec according to CPU frequency Update the per CPU cyc2ns variables in all exit pathes of tsc_calibrate. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: stable@kernel.org
* | Merge branch 'fixes' of ↵Linus Torvalds2008-05-23
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/davej/cpufreq * 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/davej/cpufreq: [CPUFREQ] clarify license of freq_table.c [CPUFREQ] Remove documentation of removed ondemand tunable. [CPUFREQ] Crusoe: longrun cpufreq module reports false min freq [CPUFREQ] powernow-k8: improve error messages
| * | [CPUFREQ] Crusoe: longrun cpufreq module reports false min freqmaximilian attems2008-05-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The longrun cpufreq module reports a false minimum frequency 3MHz on 300-600MHz Crusoe processor. This may be due to a calculation bug in the module. Original patch from Kaz Sasayama <kazssym@hypercore.co.jp> submitted as http://bugs.debian.org/468149 patch ported to x86 Cc: Kaz Sasayama <kazssym@hypercore.co.jp> Signed-off-by: maximilian attems <max@stro.at> Signed-off-by: Dave Jones <davej@redhat.com>
| * | [CPUFREQ] powernow-k8: improve error messagesMark Langsdorf2008-05-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The most common error with powernow-k8 is an ACPI _PSS error caused either by failure to load the ACPI processor module or a bad parse of the _PSS object. Make the error message returned to the user in these situations more straightforward and easier to understand. -Mark Langsdorf Operating System Research Center AMD Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com> Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> Signed-off-by: Dave Jones <davej@redhat.com>
* | | x86: fix integer as NULL pointer warningHarvey Harrison2008-05-23
| |/ |/| | | | | | | | | | | arch/x86/boot/printf.c:59:10: warning: Using plain integer as NULL pointer Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | Merge branch 'for-linus' of ↵Linus Torvalds2008-05-20
|\ \ | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6 * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: PCI: correct mailing list address PCI: Correct last two HP entries in the bfsort whitelist
| * | PCI: Correct last two HP entries in the bfsort whitelistTony Camuso2008-05-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace Redundant Whitelist Entries with the Correct Ones The ProLiant DL585 G2 and the DL585 G2 are entered reundantly in the dmi_system_id table. What should have been there are the DL360 and DL380. This patch simply replaces the redundant entries with the correct entries. Signed-off-by: Tony Camuso <tony.camuso@hp.com> Signed-off-by: Pat Schoeller <patrick.schoeller@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | Merge branch 'for-linus' of ↵Linus Torvalds2008-05-19
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs-2.6 * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs-2.6: [PATCH] return to old errno choice in mkdir() et.al. [Patch] fs/binfmt_elf.c: fix wrong return values [PATCH] get rid of leak in compat_execve() [Patch] fs/binfmt_elf.c: fix a wrong free [PATCH] avoid multiplication overflows and signedness issues for max_fds [PATCH] dup_fd() part 4 - race fix [PATCH] dup_fd() - part 3 [PATCH] dup_fd() part 2 [PATCH] dup_fd() fixes, part 1 [PATCH] take init_files to fs/file.c
| * | | [PATCH] take init_files to fs/file.cAl Viro2008-05-16
| |/ / | | | | | | | | | Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* | | Merge branch 'kvm-updates-2.6.26' of ↵Linus Torvalds2008-05-19
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/avi/kvm * 'kvm-updates-2.6.26' of git://git.kernel.org/pub/scm/linux/kernel/git/avi/kvm: KVM: LAPIC: ignore pending timers if LVTT is disabled KVM: Update MAINTAINERS for new mailing lists KVM: Fix kvm_vcpu_block() task state race KVM: ia64: Set KVM_IOAPIC_NUM_PINS to 48 KVM: ia64: fix GVMM module including position-dependent objects KVM: ia64: Define new kvm_fpreg struture to replace ia64_fpreg KVM: PIT: take inject_pending into account when emulating hlt s390: KVM guest: fix compile error KVM: x86 emulator: fix writes to registers with modrm encodings
| * | KVM: LAPIC: ignore pending timers if LVTT is disabledMarcelo Tosatti2008-05-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only use the APIC pending timers count to break out of HLT emulation if the timer vector is enabled. Certain configurations of Windows simply mask out the vector without disabling the timer. Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
| * | KVM: PIT: take inject_pending into account when emulating hltMarcelo Tosatti2008-05-18
| | | | | | | | | | | | | | | | | | | | | Otherwise hlt emulation fails if PIT is not injecting IRQ's. Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
| * | KVM: x86 emulator: fix writes to registers with modrm encodingsAvi Kivity2008-05-18
| |/ | | | | | | | | | | | | | | | | A register destination encoded with a mod=3 encoding left dst.ptr NULL. Normally we don't trap writes to registers, but in the case of smsw, we do. Fix by pointing dst.ptr at the destination register. Signed-off-by: Avi Kivity <avi@qumranet.com>
* | x86: disable mwait for AMD family 10H/11H CPUsThomas Gleixner2008-05-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous revert of 0c07ee38c9d4eb081758f5ad14bbffa7197e1aec left out the mwait disable condition for AMD family 10H/11H CPUs. Andreas Herrman said: It depends on the CPU. For AMD CPUs that support MWAIT this is wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings then depend on a clock divisor and current Pstate of the core. If all cores of a processor are in halt state (C1) the processor can enter the C1E (C1 enhanced) state. If mwait is used this will never happen. Thus HLT saves more power than MWAIT here. It might be best to switch off the mwait flag for these AMD CPU families like it was introduced with commit f039b754714a422959027cb18bb33760eb8153f0 (x86: Don't use MWAIT on AMD Family 10) Re-add the AMD families 10H/11H check and disable the mwait usage for those. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* | x86: fix crash on cpu hotplug on pat-incapable machinesAvi Kivity2008-05-17
| | | | | | | | | | | | | | | | | | | | | | pat_disable() is __init, which means it goes away after booting is complete. Unfortunately it is used by the hotplug code if the machine is not pat-capable, causing a crash. Fix by marking pat_disable() as __cpuinit. Signed-off-by: Avi Kivity <avi@qumranet.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | x86: remove mwait capability C-state checkIngo Molnar2008-05-17
|/ | | | | | | | | | | | | | | | | | | | | | | | Vegard Nossum reports: | powertop shows between 200-400 wakeups/second with the description | "<kernel IPI>: Rescheduling interrupts" when all processors have load (e.g. | I need to run two busy-loops on my 2-CPU system for this to show up). | | The bisect resulted in this commit: | | commit 0c07ee38c9d4eb081758f5ad14bbffa7197e1aec | Date: Wed Jan 30 13:33:16 2008 +0100 | | x86: use the correct cpuid method to detect MWAIT support for C states remove the functional effects of this patch and make mwait unconditional. A future patch will turn off mwait on specific CPUs where that causes power to be wasted. Bisected-by: Vegard Nossum <vegard.nossum@gmail.com> Tested-by: Vegard Nossum <vegard.nossum@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* Merge branch 'x86-fixes-for-linus' of ↵Linus Torvalds2008-05-13
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86: user_regset_view table fix for ia32 on 64-bit x86: arch/x86/mm/pat.c - fix warning x86: fix csum_partial() export x86: early_init_centaur(): use set_cpu_cap() x86: fix app crashes after SMP resume x86: wakeup.lds.S - section ordering fix x86: [VOYAGER] fix duplicate phys_cpu_present_map symbol x86/pci: fix broken ISA DMA
| * x86: user_regset_view table fix for ia32 on 64-bitRoland McGrath2008-05-13
| | | | | | | | | | | | | | | | | | | | The user_regset_view table for the 32-bit regsets on the 64-bit build had the wrong sizes for the FP regsets. This bug had no user-visible effect (just on kernel modules using the user_regset interfaces and the like). But the fix is trivial and risk-free. Signed-off-by: Roland McGrath <roland@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86: arch/x86/mm/pat.c - fix warningPranith Kumar2008-05-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | fix this warning: arch/x86/mm/pat.c: In function `phys_mem_access_prot_allowed': arch/x86/mm/pat.c:558: warning: long long unsigned int format, long unsigned int arg (arg 6) arch/x86/mm/pat.c: In function `map_devmem': arch/x86/mm/pat.c:580: warning: long long unsigned int format, long unsigned int arg (arg 6) Signed-off-by: D Pranith Kumar <bobby.prani@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86: fix csum_partial() exportIngo Molnar2008-05-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix this symbol export problem: Building modules, stage 2. MODPOST 193 modules ERROR: "csum_partial" [fs/reiserfs/reiserfs.ko] undefined! make[1]: *** [__modpost] Error 1 make: *** [modules] Error 2 This is due to a known weakness of symbol exports: if a symbol's only in-core user is an EXPORT_SYMBOL from a lib-y section, the symbol is not linked in. The solution is to move the export to x8664_ksyms_64.c - but the real solution would be to fix kbuild. Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86: early_init_centaur(): use set_cpu_cap()Andrew Morton2008-05-13
| | | | | | | | | | | | | | arch/x86/kernel/setup_64.c:954: warning: passing argument 2 of 'set_bit' from incompatible pointer type Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86: fix app crashes after SMP resumeHugh Dickins2008-05-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After resume on a 2cpu laptop, kernel builds collapse with a sed hang, sh or make segfault (often on 20295564), real-time signal to cc1 etc. Several hurdles to jump, but a manually-assisted bisect led to -rc1's d2bcbad5f3ad38a1c09861bca7e252dde7bb8259 x86: do not zap_low_mappings in __smp_prepare_cpus. Though the low mappings were removed at bootup, they were left behind (with Global flags helping to keep them in TLB) after resume or cpu online, causing the crashes seen. Reinstate zap_low_mappings (with local __flush_tlb_all) for each cpu_up on x86_32. This used to be serialized by smp_commenced_mask: that's now gone, but a low_mappings flag will do. No need for native_smp_cpus_done to repeat the zap: let mem_init zap BSP's low mappings just like on UP. (In passing, fix error code from native_cpu_up: do_boot_cpu returns a variety of diagnostic values, Dprintk what it says but convert to -EIO. And save_pg_dir separately before zap_low_mappings: doesn't matter now, but zapping twice in succession wiped out resume's swsusp_pg_dir.) That worked well on the duo and one quad, but wouldn't boot 3rd or 4th cpu on P4 Xeon, oopsing just after unlock_ipi_call_lock. The TLB flush IPI now being sent reveals a long-standing bug: the booting cpu has its APIC readied in smp_callin at the top of start_secondary, but isn't put into the cpu_online_map until just before that unlock_ipi_call_lock. So native_smp_call_function_mask to online cpus would send_IPI_allbutself, including the cpu just coming up, though it has been excluded from the count to wait for: by the time it handles the IPI, the call data on native_smp_call_function_mask's stack may well have been overwritten. So fall back to send_IPI_mask while cpu_online_map does not match cpu_callout_map: perhaps there's a better APICological fix to be made at the start_secondary end, but I wouldn't know that. Signed-off-by: Hugh Dickins <hugh@veritas.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * x86: wakeup.lds.S - section ordering fixCyrill Gorcunov2008-05-12
| | | | | | | | | | | | | | | | | | | | | | To allow linker to catch sections overlapping we have to declare them in appropriate order. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com> Cc: Sam Ravnborg <sam@ravnborg.org> Acked-by: Pavel Machek <pavel@suse.cz> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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