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* apic, x86: Use BIOS settings for IBS and MCE threshold interrupt LVT offsetsRobert Richter2010-10-19
| | | | | | | | | | | | | | | | We want the BIOS to setup the EILVT APIC registers. The offsets were hardcoded and BIOS settings were overwritten by the OS. Now, the subsystems for MCE threshold and IBS determine the LVT offset from the registers the BIOS has setup. If the BIOS setup is buggy on a family 10h system, a workaround enables IBS. If the OS determines an invalid register setup, a "[Firmware Bug]: " error message is reported. We need this change also for upcomming cpu families. Signed-off-by: Robert Richter <robert.richter@amd.com> LKML-Reference: <1286360874-1471-3-git-send-email-robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* oprofile/x86: make AMD IBS hotplug capableRobert Richter2010-05-06
| | | | | | | | | | | | Current IBS code is not hotplug capable. An offline cpu might not be initialized or deinitialized properly. This patch fixes this by removing on_each_cpu() functions. The IBS init/deinit code is executed in the per-cpu functions model->setup_ctrs() and model->cpu_down() which are also called by hotplug notifiers. model->cpu_down() replaces model->exit() that became obsolete. Cc: Andi Kleen <andi@firstfloor.org> Signed-off-by: Robert Richter <robert.richter@amd.com>
* oprofile/x86: remove duplicate IBS capability checkRobert Richter2010-05-04
| | | | | | The check is already done in ibs_exit(). Signed-off-by: Robert Richter <robert.richter@amd.com>
* oprofile/x86: move IBS codeRobert Richter2010-05-04
| | | | | | | Moving code to make future changes easier. This groups all IBS code together. Signed-off-by: Robert Richter <robert.richter@amd.com>
* oprofile/x86: return -EBUSY if counters are already reservedRobert Richter2010-05-04
| | | | | | | | In case a counter is already reserved by the watchdog or perf_event subsystem, oprofile ignored this counters silently. This case is handled now and oprofile_setup() now reports an error. Signed-off-by: Robert Richter <robert.richter@amd.com>
* oprofile/x86: moving shutdown functionsRobert Richter2010-05-04
| | | | | | Moving some code in preparation of the next patch. Signed-off-by: Robert Richter <robert.richter@amd.com>
* oprofile/x86: reserve counter msrs pairwiseRobert Richter2010-05-04
| | | | | | | | | | For AMD's and Intel's P6 generic performance counters have pairwise counter and control msrs. This patch changes the counter reservation in a way that both msrs must be registered. It joins some counter loops and also removes the unnecessary NUM_CONTROLS macro in the AMD implementation. Signed-off-by: Robert Richter <robert.richter@amd.com>
* perf, x86: rename macro in ARCH_PERFMON_EVENTSEL_ENABLERobert Richter2010-03-01
| | | | | | | | | | | | | | | For consistency reasons this patch renames ARCH_PERFMON_EVENTSEL0_ENABLE to ARCH_PERFMON_EVENTSEL_ENABLE. The following is performed: $ sed -i -e s/ARCH_PERFMON_EVENTSEL0_ENABLE/ARCH_PERFMON_EVENTSEL_ENABLE/g \ arch/x86/include/asm/perf_event.h arch/x86/kernel/cpu/perf_event.c \ arch/x86/kernel/cpu/perf_event_p6.c \ arch/x86/kernel/cpu/perfctr-watchdog.c \ arch/x86/oprofile/op_model_amd.c arch/x86/oprofile/op_model_ppro.c Signed-off-by: Robert Richter <robert.richter@amd.com>
* perf, x86: add some IBS macros to perf_event.hRobert Richter2010-03-01
| | | | Signed-off-by: Robert Richter <robert.richter@amd.com>
* perf, x86: make IBS macros available in perf_event.hRobert Richter2010-03-01
| | | | | | | This patch moves code from oprofile to perf_event.h to make it also available for usage by perf. Signed-off-by: Robert Richter <robert.richter@amd.com>
* oprofile/x86: fix msr access to reserved countersRobert Richter2010-02-26
| | | | | | | | | During switching virtual counters there is access to perfctr msrs. If the counter is not available this fails due to an invalid address. This patch fixes this. Cc: stable@kernel.org Signed-off-by: Robert Richter <robert.richter@amd.com>
* oprofile/x86: use kzalloc() instead of kmalloc()Robert Richter2010-02-26
| | | | | Cc: stable@kernel.org Signed-off-by: Robert Richter <robert.richter@amd.com>
* oprofile/x86: fix perfctr nmi reservation for mulitplexingRobert Richter2010-02-26
| | | | | | | | | | Multiple virtual counters share one physical counter. The reservation of virtual counters fails due to duplicate allocation of the same counter. The counters are already reserved. Thus, virtual counter reservation may removed at all. This also makes the code easier. Cc: stable@kernel.org Signed-off-by: Robert Richter <robert.richter@amd.com>
* oprofile/x86: warn user if a counter is already activeRobert Richter2010-02-26
| | | | | | | | | | | This patch generates a warning if a counter is already active. Implemented for AMD and P6 models. P4 is not supported. Cc: Naga Chumbalkar <nagananda.chumbalkar@hp.com> Cc: Shashi Belur <shashi-kiran.belur@hp.com> Cc: Tony Jones <tonyj@suse.de> Signed-off-by: Robert Richter <robert.richter@amd.com>
* oprofile/x86: implement randomization for IBS periodic op counterRobert Richter2010-02-26
| | | | | | | | | | | | | | | | | | | | | | IBS selects an op (execution operation) for sampling by counting either cycles or dispatched ops. Better statistical samples can be produced by adding a software generated random offset to the periodic op counter value with each sample. This patch adds software randomization to the IBS periodic op counter. The lower 12 bits of the 20 bit counter are randomized. IbsOpCurCnt is initialized with a 12 bit random value. There is a work around if the hw can not write to IbsOpCurCnt. Then the lower 8 bits of the 16 bit IbsOpMaxCnt [15:0] value are randomized in the range of -128 to +127 by adding/subtracting an offset to the maximum count (IbsOpMaxCnt). The linear feedback shift register (LFSR) algorithm is used for pseudo-random number generation to have low impact to the memory system. Signed-off-by: Robert Richter <robert.richter@amd.com>
* oprofile/x86: implement lsfr pseudo-random number generator for IBSSuravee Suthikulpanit2010-02-26
| | | | | | | | | | | | | | | | | | | This patch implements a linear feedback shift register (LFSR) for pseudo-random number generation for IBS. For IBS measurements it would be good to minimize memory traffic in the interrupt handler since every access pollutes the data caches. Computing a maximal period LFSR just needs shifts and ORs. The LFSR method is good enough to randomize the ops at low overhead. 16 pseudo-random bits are enough for the implementation and it doesn't matter that the pattern repeats with a fairly short cycle. It only needs to break up (hard) periodic sampling behavior. The logic was designed by Paul Drongowski. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Robert Richter <robert.richter@amd.com>
* oprofile/x86: implement IBS cpuid feature detectionRobert Richter2010-02-26
| | | | | | | | | | | | | | | | | | | | This patch adds IBS feature detection using cpuid flags. An IBS capability mask is introduced to test for certain IBS features. The bit mask is the same as for IBS cpuid feature flags (Fn8000_001B_EAX), but bit 0 is used to indicate the existence of IBS. The patch also changes the handling of the IbsOpCntCtl bit (periodic op counter count control). The oprofilefs file for this feature (ibs_op/dispatched_ops) will be only exposed if the feature is available, also the default for the bit is set to count clock cycles. In general, the userland can detect the availability of a feature by checking for the corresponding file in oprofilefs. If it exists, the feature also exists. This may lead to a dynamic file layout depending on the cpu type with that the userland has to deal with. Current opcontrol is compatible. Signed-off-by: Robert Richter <robert.richter@amd.com>
* oprofile/x86: remove node check in AMD IBS initializationRobert Richter2010-02-26
| | | | | | | | | | | | Standard AMD systems have the same number of nodes as there are northbridge devices. However, there may kernel configurations (especially for 32 bit) or system setups exist, where the node number is different or it can not be detected properly. Thus the check is not reliable and may fail though IBS setup was fine. For this reason it is better to remove the check. Cc: stable <stable@kernel.org> Signed-off-by: Robert Richter <robert.richter@amd.com>
* oprofile/x86: remove OPROFILE_IBS config optionRobert Richter2010-02-26
| | | | | | | | | | OProfile support for IBS is now for several versions in the kernel. The feature is stable now and the code can be activated permanently. As a side effect IBS now works also on nosmp configs. Signed-off-by: Robert Richter <robert.richter@amd.com>
* arch/x86/oprofile/op_model_amd.c: fix op_amd_handle_ibs() return typeAndrew Morton2009-08-04
| | | | | | | | | | | arch/x86/oprofile/op_model_amd.c: In function 'op_amd_handle_ibs': arch/x86/oprofile/op_model_amd.c:217: warning: no return statement in function returning non-void Fix this by making op_amd_handle_ibs() return void. Cc: Robert Richter <robert.richter@amd.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Robert Richter <robert.richter@amd.com>
* Revert "x86: oprofile/op_model_amd.c set return values for op_amd_handle_ibs()"Robert Richter2009-08-04
| | | | | | | | This reverts commit 21e70878215f620fe99ea7d7c74bc641aeec932f. Instead Andrew's patch will be applied he posted at the same time. Signed-off-by: Robert Richter <robert.richter@amd.com>
* x86/oprofile: Small coding style fixesRobert Richter2009-07-20
| | | | | | Some small coding style fixes. Signed-off-by: Robert Richter <robert.richter@amd.com>
* x86/oprofile: Implement op_x86_virt_to_phys()Robert Richter2009-07-20
| | | | | | | This patch implements a common x86 function to convert virtual counter numbers to physical. Signed-off-by: Robert Richter <robert.richter@amd.com>
* x86/oprofile: Remove unused num_virt_controls from struct op_x86_model_specRobert Richter2009-07-20
| | | | | | | The member num_virt_controls of struct op_x86_model_spec is not used. This patch removes it. Signed-off-by: Robert Richter <robert.richter@amd.com>
* x86/oprofile: Remove const qualifier from struct op_x86_model_specRobert Richter2009-07-20
| | | | | | | This patch removes the const qualifier from struct op_x86_model_spec to make model parameters changable. Signed-off-by: Robert Richter <robert.richter@amd.com>
* oprofile: Grouping multiplexing code in op_model_amd.cRobert Richter2009-07-20
| | | | | | | | This patch moves some multiplexing code to the new function op_mux_fill_in_addresses(). Also, the whole multiplexing code is now at a single location. Signed-off-by: Robert Richter <robert.richter@amd.com>
* oprofile: Introduce op_x86_phys_to_virt()Robert Richter2009-07-20
| | | | | | This new function translates physical to virtual counter numbers. Signed-off-by: Robert Richter <robert.richter@amd.com>
* x86/oprofile: Fix usage of NUM_CONTROLS/NUM_COUNTERS macrosRobert Richter2009-07-20
| | | | | | | | Use the corresponding macros when iterating over counter and control registers. Since NUM_CONTROLS and NUM_COUNTERS are equal for AMD cpus the fix is more a cosmetical change. Signed-off-by: Robert Richter <robert.richter@amd.com>
* oprofile: Implement performance counter multiplexingJason Yeh2009-07-20
| | | | | | | | | | | | | | | | | | | | | The number of hardware counters is limited. The multiplexing feature enables OProfile to gather more events than counters are provided by the hardware. This is realized by switching between events at an user specified time interval. A new file (/dev/oprofile/time_slice) is added for the user to specify the timer interval in ms. If the number of events to profile is higher than the number of hardware counters available, the patch will schedule a work queue that switches the event counter and re-writes the different sets of values into it. The switching mechanism needs to be implemented for each architecture to support multiplexing. This patch only implements AMD CPU support, but multiplexing can be easily extended for other models and architectures. There are follow-on patches that rework parts of this patch. Signed-off-by: Jason Yeh <jason.yeh@amd.com> Signed-off-by: Robert Richter <robert.richter@amd.com>
* x86/oprofile: Whitespaces changes onlyRobert Richter2009-07-14
| | | | | | | This patch fixes whitespace changes of code that will be touched in follow-on patches. Signed-off-by: Robert Richter <robert.richter@amd.com>
* x86/oprofile: Fix cast of counter valueRobert Richter2009-07-14
| | | | | | | | When casting the counter value to a 64 bit value in 32 bit mode, sign extension may lead to broken counter values. This patch fixes this by casting to (u64) instead of (s64). Signed-off-by: Robert Richter <robert.richter@amd.com>
* x86: oprofile/op_model_amd.c set return values for op_amd_handle_ibs()Jaswinder Singh Rajput2009-06-18
| | | | | | | | | | | | op_amd_handle_ibs() should return 0 when IBS is not present or not defined. Fix compilation warning: CC [M] arch/x86/oprofile/op_model_amd.o arch/x86/oprofile/op_model_amd.c: In function ‘op_amd_handle_ibs’: arch/x86/oprofile/op_model_amd.c:217: warning: no return statement in function returning non-void Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com> Signed-off-by: Robert Richter <robert.richter@amd.com>
* x86/oprofile: introduce oprofile_add_data64()Robert Richter2009-06-11
| | | | | | | | | The IBS implemention writes 64 bit register values to the cpu buffer by writing two 32 values using oprofile_add_data(). This patch introduces oprofile_add_data64() to write a single 64 bit value to the buffer. Signed-off-by: Robert Richter <robert.richter@amd.com>
* x86/oprofile: use 64 bit values in IBS functionsRobert Richter2009-06-11
| | | | | | | | | | The IBS code internally uses 32 bit values (a low and a high value) to represent a 64 bit value. This patch changes this and now 64 bit values are used instead. 64 bit MSR functions can be used now. No functional changes. Signed-off-by: Robert Richter <robert.richter@amd.com>
* x86/oprofile: use 64 bit wrmsr functionsRobert Richter2009-06-11
| | | | | | This patch replaces some wrmsr() functions with wrmsrl(). Signed-off-by: Robert Richter <robert.richter@amd.com>
* x86/oprofile: replace CTR*_IS_RESERVED macrosRobert Richter2009-06-11
| | | | | | The patch replaces all CTR*_IS_RESERVED macros. Signed-off-by: Robert Richter <robert.richter@amd.com>
* x86/oprofile: replace CTRL_SET_*ACTIVE macrosRobert Richter2009-06-11
| | | | | | | | The patch replaces all CTRL_SET_*ACTIVE macros. 64 bit MSR functions and 64 bit counter values are used now. The code uses bit masks from <asm/intel_arch_perfmon.h>. Signed-off-by: Robert Richter <robert.richter@amd.com>
* x86/oprofile: replace CTR_OVERFLOWED macrosRobert Richter2009-06-11
| | | | | | | | The patch replaces all CTR_OVERFLOWED macros. 64 bit MSR functions and 64 bit counter values are used now. Thus, it will be easier to later extend the models to use more than 32 bit width counters. Signed-off-by: Robert Richter <robert.richter@amd.com>
* x86/oprofile: replace macros to calculate control registerRobert Richter2009-06-11
| | | | | | | | | | | | | This patch introduces op_x86_get_ctrl() to calculate the value of the performance control register. This is generic code usable for all models. The event and reserved masks are model specific and stored in struct op_x86_model_spec. 64 bit MSR functions are used now. The patch removes many hard to read macros used for ctrl calculation. The function op_x86_get_ctrl() is common code and the first step to further merge performance counter implementations for x86 models. Signed-off-by: Robert Richter <robert.richter@amd.com>
* x86/oprofile: pass the model to setup_ctrs() functionsRobert Richter2009-06-11
| | | | | | | | In follow-on patches the setup_ctrs() functions will need data that describes the model. This patch extends the function argument list to pass a pointer of the model to these function. Signed-off-by: Robert Richter <robert.richter@amd.com>
* x86/oprofile: remove unused macros for AMD virtualization profilingRobert Richter2009-06-11
| | | | | | | The use of the macros has no effect. The oprofilefs has to be extended first to support these features. Signed-off-by: Robert Richter <robert.richter@amd.com>
* x86/oprofile: remove MSR macros for AMD cpusRobert Richter2009-06-11
| | | | | | | | The macros CTRL_READ() and CTRL_WRITE() make the code hard to read and maintain. This patch replaces them by rdmsr()/wrmsr() functions and simplifies the code. Signed-off-by: Robert Richter <robert.richter@amd.com>
* x86/oprofile: move common macros to op_x86_model.hRobert Richter2009-06-11
| | | | | | | There are duplicate macro implementations in model specific code. This patch moves all common macros to op_x86_model.h. Signed-off-by: Robert Richter <robert.richter@amd.com>
* x86/oprofile: remove #ifdefs in ibs functionsRobert Richter2009-06-11
| | | | | | | IBS code is moved to separate functions. This allows the removal of #ifdefs in functions. Signed-off-by: Robert Richter <robert.richter@amd.com>
* oprofile: make new cpu buffer functions part of the apiRobert Richter2009-01-07
| | | | | | | | | | | | This patch creates the new functions oprofile_write_reserve() oprofile_add_data() oprofile_write_commit() and makes them part of the oprofile api. Signed-off-by: Robert Richter <robert.richter@amd.com>
* oprofile: use new data sample format for ibsRobert Richter2009-01-07
| | | | | | | | | | | | | The new ring buffer implementation allows the storage of samples with different size. This patch implements the usage of the new sample format to store ibs samples in the cpu buffer. Until now, writing to the cpu buffer could lead to incomplete sampling sequences since IBS samples were transfered in multiple samples. Due to a full buffer, data could be lost at any time. This can't happen any more since the complete data is reserved in advance and then stored in a single sample. Signed-off-by: Robert Richter <robert.richter@amd.com>
* oprofile: rework implementation of cpu buffer eventsRobert Richter2009-01-07
| | | | | | | | | | | | | | | | | Special events such as task or context switches are marked with an escape code in the cpu buffer followed by an event code or a task identifier. There is one escape code per event. To make escape sequences also available for data samples the internal cpu buffer format must be changed. The current implementation does not allow the extension of event codes since this would lead to collisions with the task identifiers. To avoid this, this patch introduces an event mask that allows the storage of multiple events with one escape code. Now, task identifiers are stored in the data section of the sample. The implementation also allows the usage of custom data in a sample. As a side effect the new code is much more readable and easier to understand. Signed-off-by: Robert Richter <robert.richter@amd.com>
* oprofile: rename variable ibs_allowed to has_ibs in op_model_amd.cRobert Richter2009-01-07
| | | | | | | This patch renames ibs_allowed to has_ibs. Varible name fits better now. Signed-off-by: Robert Richter <robert.richter@amd.com>
* x86/oprofile: fix pci_dev use count for AMD northbridge devicesRobert Richter2008-12-29
| | | | | | | | | | | This patch fixes the PCI device use count for AMD northbridge devices. In case of an IBS LVT initialization failure, the PCI device is released now by calling pci_dev_put(). If there are no initialization errors, the devices are released in pci_get_device() while iterating. Signed-off-by: Robert Richter <robert.richter@amd.com>
* x86/oprofile: cleanup IBS init/exit functions in op_model_amd.cRobert Richter2008-12-10
| | | | | | | | Implementation of pairwise init/exit funcions for IBS and IBS NMI setup. There are also some function renames and the removal of forward function declarations. Signed-off-by: Robert Richter <robert.richter@amd.com>
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