| Commit message (Collapse) | Author | Age | |
|---|---|---|---|
| * | [SPARC64]: store-init needs trailing membar. | David S. Miller | 2007-03-19 |
| | | | | | | | | | | | | | | | | | The manual says that it is required and we actually have crash reports where loads see stale data due to not having membars here. In one case the networking does: memset(skb, 0, offsetof(struct sk_buff, truesize)); and then some code later checks skb->nohdr for zero, but it's still the value that was there before the memset(). Note that arch/sparc64/lib/xor.S already got this right. Signed-off-by: David S. Miller <davem@davemloft.net> | ||
| * | [SPARC64]: Optimized TSB table initialization. | David S. Miller | 2006-03-20 |
| | | | | | | | | | | | | | | | We only need to write an invalid tag every 16 bytes, so taking advantage of this can save many instructions compared to the simple memset() call we make now. A prefetching implementation is implemented for sun4u and a block-init store version if implemented for Niagara. The next trick is to be able to perform an init and a copy_tsb() in parallel when growing a TSB table. Signed-off-by: David S. Miller <davem@davemloft.net> | ||
| * | [SPARC64]: Niagara optimized memset/bzero/clear_user. | David S. Miller | 2006-03-20 |
| Signed-off-by: David S. Miller <davem@davemloft.net> | |||
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index : litmus-rt.git | |
| The LITMUS^RT kernel. | Bjoern Brandenburg |
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