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* [SPARC64]: Do not expand CHEETAH_LOG_ERROR 3 times.David S. Miller2005-08-30
| | | | | | | We only need to expand this thing once, saving some text section space. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Revamp Spitfire error trap handling.David S. Miller2005-08-29
| | | | | | | | | | | | | | | | | | | Current uncorrectable error handling was poor enough that the processor could just loop taking the same trap over and over again. Fix things up so that we at least get a log message and perhaps even some register state. In the process, much consolidation became possible, particularly with the correctable error handler. Prefix assembler and C function names with "spitfire" to indicate that these are for Ultra-I/II/IIi/IIe only. More work is needed to make these routines robust and featureful to the level of the Ultra-III error handlers. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Do not call winfix_dax blindlyDavid S. Miller2005-08-29
| | | | | | | | | Verify we really are taking a data access exception trap, at TL1, from one of the window spill/fill handlers. Else call a new function, data_access_exception_tl1, to log the error. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix trap state reading for instruction_access_exception.David S. Miller2005-08-29
| | | | | | | | | | 1) Read ASI_IMMU SFSR not ASI_DMMU. 2) IMMU has no SFAR, read TPC instead 3) Delete old and incorrect comment about the DTLB protection trap having a dependency on the SFSR contents in order to function correctly Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Move syscall success and newchild state out of thread flags.David S. Miller2005-07-24
| | | | | | | | | These two bits were accesses non-atomically from assembler code. So, in order to eliminate any potential races resulting from that, move these pieces of state into two bytes elsewhere in struct thread_info. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add syscall auditing support.David S. Miller2005-07-10
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Pass regs and entry/exit boolean to syscall_trace()David S. Miller2005-07-10
| | | | | | | | Also fix a bug in 32-bit syscall tracing. We forgot to update this code when we moved over to the convention that all 32-bit syscall arguments are zero extended by default. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add SECCOMP support.David S. Miller2005-07-10
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill ancient and unused SYSCALL_TRACING debugging code.David S. Miller2005-07-10
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add support for IRQ pre-handlers.David S. Miller2005-07-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows a PCI controller to shim into IRQ delivery so that DMA queues can be drained, if necessary. If some bus specific code needs to run before an IRQ handler is invoked, the bus driver simply needs to setup the function pointer in bucket->irq_info->pre_handler and the two args bucket->irq_info->pre_handler_arg[12]. The Schizo PCI driver is converted over to use a pre-handler for the DMA write-sync processing it needs when a device is behind a PCI->PCI bus deeper than the top-level APB bridges. While we're here, clean up all of the action allocation and handling. Now, we allocate the irqaction as part of the bucket->irq_info area. There is an array of 4 irqaction (for PCI irq sharing) and a bitmask saying which entries are active. The bucket->irq_info is allocated at build_irq() time, not at request_irq() time. This simplifies request_irq() and free_irq() tremendously. The SMP dynamic IRQ retargetting code got removed in this change too. It was disabled for a few months now, and we can resurrect it in the future if we want. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Get rid of fast IRQ feature.David S. Miller2005-06-27
| | | | | | | | | | | The only real user was the assembler floppy interrupt handler, which does not need to be in assembly. This makes it so that there are less pieces of code which know about the internal layout of ivector_table[] and friends. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Avoid membar instructions in delay slots.David S. Miller2005-06-27
| | | | | | | | | | | | | | | | | | | | In particular, avoid membar instructions in the delay slot of a jmpl instruction. UltraSPARC-I, II, IIi, and IIe have a bug, documented in the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51 The long and short of it is that if the IMU unit misses on a branch or jmpl, and there is a store buffer synchronizing membar in the delay slot, the chip can stop fetching instructions. If interrupts are enabled or some other trap is enabled, the chip will unwedge itself, but performance will suffer. We already had a workaround for this bug in a few spots, but it's better to have the entire tree sanitized for this rule. Signed-off-by: David S. Miller <davem@davemloft.net>
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-16
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!