| Commit message (Collapse) | Author | Age |
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Hand off the user LEDs to the heartbeat driver.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This permits the resource access size to be handed off through the
resource flags, which saves platforms from having to establish
platform data only to specify the register width.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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The last commit introduced the following breakage
arch/sh/include/asm/mmu.h: In function 'pmb_remap':
arch/sh/include/asm/mmu.h:79: error: expected ';' before '}' token
and...
arch/sh/include/asm/mmu.h:78: error: 'EINVAL' undeclared (first use in this function)
arch/sh/include/asm/mmu.h:78: error: (Each undeclared identifier is reported only once
arch/sh/include/asm/mmu.h:78: error: for each function it appears in.)
arch/sh/include/asm/mmu.h: In function 'pmb_init':
arch/sh/include/asm/mmu.h:87: error: 'ENODEV' undeclared (first use in this function)
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This stubs in some preliminary board support for the RTE SDK7786.
This is quite stunted at the moment, and primarily builds on top of the
system FPGA. FPGA IRQs are handled via CPU IRL masking for simplicity,
with initial peripheral support restricted to the debug ethernet.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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These were originally named _nopmd and _pmd to follow their asm-generic
counterparts, but we rename them to -2level and -3level for general
consistency.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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All SH-X2 and SH-X3 parts support an extended TLB mode, which has been
left as experimental since support was originally merged. Now that it's
had some time to stabilize and get some exposure to various platforms,
we can drop it as an option and default enable it across the board.
This is also good future proofing for newer parts that will drop support
for the legacy TLB mode completely.
This will also force 3-level page tables for all newer parts, which is
necessary both for the varying page sizes and larger memories.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This stubs out all of the PxSEGADDR() wrappers for non-legacy code.
29-bit will continue to work with these, while 32-bit code will now blow
up on compile rather than at runtime.
The vast majority of the in-tree offenders are gone, with the only
remaining culprits being unable to support 32-bit mode.
Hopefully this will prevent anyone from ever using these again.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Valid sizes include 256kB, not 258kB.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This introduces some much overdue chainsawing of the fixed PMB support.
fixed PMB was introduced initially to work around the fact that dynamic
PMB mode was relatively broken, though they were never intended to
converge. The main areas where there are differences are whether the
system is booted in 29-bit mode or 32-bit mode, and whether legacy
mappings are to be preserved. Any system booting in true 32-bit mode will
not care about legacy mappings, so these are roughly decoupled.
Regardless of the entry point, PMB and 32BIT are directly related as far
as the kernel is concerned, so we also switch back to having one select
the other.
With legacy mappings iterated through and applied in the initialization
path it's now possible to finally merge the two implementations and
permit dynamic remapping overtop of remaining entries regardless of
whether boot mappings are crafted by hand or inherited from the boot
loader.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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The mass produced cuts use an updated PVR value, add them to the list.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This makes vmlinux.bin generation an explicit make target, as opposed to
just a dependency for some of the other targets.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Plugs in LZO along with the others.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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All SH CPUs (with the exception of sh64) support the UBC, so select
HW_BREAKPOINT support by default. This fixes up the build for non-SH4A
targets.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This was used by the old hw-breakpoints API, but now there is nothing
is using it anymore, so just kill it off.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Nothing is using these now, so kill them all off.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This is the next big chunk of hw_breakpoint support. This decouples
the SH-4A support from the core and moves it out in to its own stub,
following many of the conventions established with the perf events
layering.
In addition to extending SH-4A support to encapsulate the remainder
of the UBC channels, clock framework support for handling the UBC
interface clock is added as well, allowing for dynamic clock gating.
This also fixes up a regression introduced by the SIGTRAP handling that
broke the ksym_tracer, to the extent that the current support works well
with all of the ksym_tracer/ptrace/kgdb. The kprobes singlestep code will
follow in turn.
With this in place, the remaining UBC variants (SH-2A and SH-4) can now
be trivially plugged in.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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SH-2A was referencing the old handler that no longer exists, fix it up.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This is the initial step for converting singlestep handling via ptrace
over to hw_breakpoints.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This kills off kgdb's breakpoint handler and ties in to the notifier
chain instead.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Presently the hw_breakpoint code is the primary notifier dispatch for
breakpoint traps, although it's only UBC traps that are of particular
interest there. This patches in a check to allow non-UBC generated
breakpoints to pass through down the remainder of the notifier chain,
giving things like kgdb a chance at getting notified.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This follows the x86 change to select perf events when hw_breakpoint
support is enabled. This fixes up build issues where perf events can
otherwise be disabled on their own.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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The event callback handling has been removed in favour of going through a
generic event handler to handle overflows. Follows the x86 change.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Conflict between FPU thread flag migration and debug
thread flag addition.
Conflicts:
arch/sh/include/asm/thread_info.h
arch/sh/include/asm/ubc.h
arch/sh/kernel/process_32.c
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This adds preliminary support for the SH-4A UBC to the hw-breakpoints API.
Presently only a single channel is implemented, and the ptrace interface
still needs to be converted. This is the first step to cleaning up the
long-standing UBC mess, making the UBC more generally accessible, and
finally making it SMP safe.
An additional abstraction will be layered on top of this as with the perf
events code to permit the various CPU families to wire up support for
their own specific UBCs, as many variations exist.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This follows the x86 xstate changes and implements a task_xstate slab
cache that is dynamically sized to match one of hard FP/soft FP/FPU-less.
This also tidies up and consolidates some of the SH-2A/SH-4 FPU
fragmentation. Now fpu state restorers are commonly defined, with the
init_fpu()/fpu_init() mess reworked to follow the x86 convention.
The fpu_init() register initialization has been replaced by xstate setup
followed by writing out to hardware via the standard restore path.
As init_fpu() now performs a slab allocation a secondary lighterweight
restorer is also introduced for the context switch.
In the future the DSP state will be rolled in here, too.
More work remains for math emulation and the SH-5 FPU, which presently
uses its own special (UP-only) interfaces.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Presently this has a BUG_ON() for failure cases, as powerpc does. Switch
this over to a SLAB_PANIC instead.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Presently the thread_info allocators are special cased, depending on
THREAD_SHIFT < PAGE_SHIFT. This provides a sensible definition for them
regardless of configuration, in preparation for extended CPU state.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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start_thread() will become a bit heavier with the xstate freeing to be
added in, so move it out-of-line in preparation.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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The legacy P2 area may not always be mapped (for example when using
PMB). So perform an icbi on an address that we know will always be
mapped.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This adds some VBR sanity checks in the sh_bios code to ensure that the
BIOS VBR is in range before blindly trapping in to it. This permits
boards with varying boot loader configurations to always leave support
for sh-bios enabled and it will just be disabled at run-time if not
found.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This splits out the unaligned access counters and userspace bits in to
their own generic interface, which will allow them to be wired up on sh64
too.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Now that the sh-sci earlyprintk is taken care of by the sh-sci driver
directly, there's no longer any reason for having a split-out
early_printk framework. sh_bios is the only other thing that uses it, so
we just migrate the leftovers in to there. As it's possible to have
multiple early_param()'s for the same string, there's not much point in
having this split out anymore anyways, particularly since the sh_bios
dependencies are still special-cased within sh-sci itself.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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sh_bios_char_out() is not used by anything in-tree these days, so just
get rid of it.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This was conditionalized on CONFIG_EARLY_PRINTK, which has subsequently
gone away. Now that the serial driver always supports the early console,
make sure we always establish the mapping.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This moves the VBR handling out of the main trap handling code and in to
the sh-bios helper code. A couple of accessors are added in order to
permit other kernel code to get at the VBR value for state save/restore
paths.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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As SH has a very sparse IRQ map by default, all new CPUs and boards
benefit from using sparseirq by default. Despite this, there are still a
few stragglers (mostly due to using a fixed IRQ range for their FPGA
IRQ mappings), and these still need to be converted over one by one. As
these are now in the minority, and we do not want to encourage this sort
of brain-damage in newer board ports, we force sparseirq on.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This gets rid of the arbitrary set of vectors used by the SE7722 FPGA
interrupt controller and switches over to a completely dynamic set.
No assumptions regarding a contiguous range are made, and the platform
resources themselves need to be filled in lazily.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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The LL/SC and IRQ versions were using generic stubs while the GRB version
was just reimplementing what it already had for the standard cmpxchg()
code. As we have optimized cmpxchg() implementations that are decoupled
from the atomic code, simply falling back on the generic wrapper does the
right thing. With this in place the GRB case is unaffected while the
LL/SC case gets to use its optimized cmpxchg().
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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pgtable_cache_init() has been moved out-of-line, so we also need a dummy
definition for it on nommu to fix up the build.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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We previously had 2 quicklists, one for the PGD case and one for PTEs.
Now that the PGD/PMD cases are handled through slab caches due to the
multi-level configurability, only the PTE quicklist remains. As such,
reduce NR_QUICK to its appropriate size and bump down the PTE quicklist
index.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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We also switched away from quicklists and instead moved to slab
caches. After benchmarking both implementations the difference is
negligible. The slab caches suit us better though because the size of a
pgd table is just 4 entries when we're using a 3-level page table layout
and quicklists always deal with pages.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
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If the page is not mapped into any process's address space then aliases
cannot exist in the cache. So reduce the amount of flushing we perform.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
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The previous expressions were wrong which made free_pmd_range() explode
when using anything other than 4KB pages (which is why 8KB and 64KB
pages were disabled with the 3-level page table layout).
The problem was that pmd_offset() was returning an index of non-zero
when it should have been returning 0. This non-zero offset was used to
calculate the address of the pmd table to free in free_pmd_range(),
which ended up trying to free an object that was not aligned on a page
boundary.
Now 3-level page tables should work with 4KB, 8KB and 64KB pages.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
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Apply some TLC to the SH64 header files and remove some functions that
are not used anymore.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
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