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* sh: add probe support for new sh7722 cutMagnus Damm2008-02-14
| | | | | | | This patch adds support for sh7722 devices with prr value 0xa1. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* Fix container_of() usageAlexey Dobriyan2008-02-08
| | | | | | | | | | Using "attr" twice is not OK, because it effectively prohibits such container_of() on variables not named "attr". Signed-off-by: Alexey Dobriyan <adobriyan@sw.ru> Acked-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* sh: Add OHCI and UDC platform devices for SH7720.Yoshihiro Shimoda2008-01-27
| | | | | Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: intc - remove default interrupt priority tablesMagnus Damm2008-01-27
| | | | | | | | | | | | | This patch removes interrupt priority tables from the intc code. Optimal priority assignment varies with embedded application anyway, so keeping the interrupt priority tables together with cpu-specific code doesn't make sense. The function intc_set_priority() should be used instead to set the desired interrupt priority level. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: sh7712 clock supportAndrew Murray2008-01-27
| | | | | | | This patch provides specific clock support for the SH7712. Signed-off-by: Andrew Murray <amurray@mpc-data.co.uk> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Add support for SH7763 CPU subtype.Yoshihiro Shimoda2008-01-27
| | | | | Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Add support for SH7721 CPU subtype.Yoshihiro Shimoda2008-01-27
| | | | | Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Encode L1/L2 cache shape in auxvt.Paul Mundt2008-01-27
| | | | | | | | | This adds in the L1I/L1D/L2 cache shape support to their respective entries in the ELF auxvt, based on the Alpha implementation. We use this on the userspace libc side for calculating a tightly packed SHMLBA amongst other things. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Support denormalization on SH-4 FPU.Stuart Menefy2008-01-27
| | | | | Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Preparation for uncached jumps through PMB.Stuart Menefy2008-01-27
| | | | | | | | | | | | Presently most of the 29-bit physical parts do P1/P2 segmentation with a 1:1 cached/uncached mapping, jumping between the two to control the caching behaviour. This provides the basic infrastructure to maintain this behaviour on 32-bit physical parts that don't map P1/P2 at all, using a shiny new linker section and corresponding fixmap entry. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: GUSA atomic rollback support.Stuart Menefy2008-01-27
| | | | | | | | | | This implements kernel-level atomic rollback built on top of gUSA, as an alternative non-IRQ based atomicity method. This is generally a faster method for platforms that are lacking the LL/SC pairs that SH-4A and later use, and is only supportable on legacy cores. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: comment tidying for sh64->sh migration.Paul Mundt2008-01-27
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: syscall auditing for sh5, too.Paul Mundt2008-01-27
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: SH-2A FPU support.Paul Mundt2008-01-27
| | | | | Signed-off-by: Kieran Bingham <kbingham@mpc-data.co.uk> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Add SH7263 CPU support.Paul Mundt2008-01-27
| | | | | | | | | | | | This adds support for the SH7263 (SH-2A) CPU. This particular CPU is a superset of SH7203, adding some additional peripheral blocks and hooking up additional (reserved on SH7203) vectors in the INTC block. No visibly nasty surprises, yet.. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Add SH7203 CPU support.Paul Mundt2008-01-27
| | | | | | | This adds support for the SH7203 (SH-2A) CPU. Signed-off-by: Kieran Bingham <kbingham@mpc-data.co.uk> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Bring the SH-5 FPU in line with the SH-4 FPU API.Paul Mundt2008-01-27
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Get the mach-cayman IRQ support building.Paul Mundt2008-01-27
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Switch SH-5 to use CONFIG_PAGE_OFFSET.Paul Mundt2008-01-27
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Stub in CPU subtype setup code for SH5-101/103.Paul Mundt2008-01-27
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Plug in simple SH-5 subtype probing.Paul Mundt2008-01-27
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Kill off do_NMI stub in SH-5 ex table.Paul Mundt2008-01-27
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Share bug/debug traps across _32 and _64.Paul Mundt2008-01-27
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Move over and enable FPU support for SH-5.Paul Mundt2008-01-27
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Move over sh64 switch_to and stack unwinder.Paul Mundt2008-01-27
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Move over the SH-5 entry.S.Paul Mundt2008-01-27
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Disable initial cache flush on SH-5.Paul Mundt2008-01-27
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Don't reference UBC code in CPU init on sh64.Paul Mundt2008-01-27
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: imask IRQ depends on sh32.Paul Mundt2008-01-27
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* Kobject: convert arch/* from kobject_unregister() to kobject_put()Greg Kroah-Hartman2008-01-24
| | | | | | | | | | | There is no need for kobject_unregister() anymore, thanks to Kay's kobject cleanup changes, so replace all instances of it with kobject_put(). Cc: Kay Sievers <kay.sievers@vrfy.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* Kobject: change arch/sh/kernel/cpu/sh4/sq.c to use kobject_init_and_addGreg Kroah-Hartman2008-01-24
| | | | | | | | | Stop using kobject_register, as this way we can control the sending of the uevent properly, after everything is properly initialized. Cc: Kay Sievers <kay.sievers@vrfy.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* sh: Kill off the remaining ST40 cruft.Paul Mundt2007-11-06
| | | | | | | | | | | | | The ST40 stuff in-tree hasn't built for some time, and hasn't been updated for over 3 years. ST maintains their own out-of-tree changes and rebases occasionally, and that's ultimately where all of the ST40 users go anyways. In order for the ST40 code to be brought up to date most of the stuff removed in this changeset would have to be rewritten anyways, so there's very little benefit in keeping the remnants around either. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fix up kgdb-on-NMI branch target.Paul Mundt2007-11-06
| | | | | | | | | This was all reworked some time ago, the old debug_enter was ripped out with everything going through a debug trap jump table instead. Kill off the debug_enter target and reference kgdb_handle_exception directly. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Kill off dead ipr_irq_demux().Paul Mundt2007-10-31
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Add resource of USBF for SH7722.Yoshihiro Shimoda2007-10-30
| | | | | Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: clkfwk: Support multi-level clock propagation.Stuart Menefy2007-09-27
| | | | | | | | Currently clock propagation only works for one level, but we have some clocks which need to propagate multiple levels, so make this recursive. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fix URAM start address on SH7785.Paul Mundt2007-09-27
| | | | | | | | Not all of the SH-X2 URAM blocks are mapped in the same place, SH7785 happens to map it on the opposite end of the address space from SH7722, correct the addresses. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Use boot_cpu_data for CPU probe.Paul Mundt2007-09-27
| | | | | | | | | | This moves off of smp_processor_id() and only sets the probe information for the boot CPU directly. This will be copied out for the secondaries, so there's no reason to do this each time. This also allows for some header tidying. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fix plat_irq_setup_pins() for SH7785.Paul Mundt2007-09-27
| | | | | | | There was some debug code left in here that caused the pin changes to never be hit. Kill that off, and all is well. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Disable L2 reporting for present URAM only parts.Paul Mundt2007-09-26
| | | | | | | | | The probing logic works for both URAM and L2, with no way to distinguish between the two. Disable the probing for now and let the CPU subtypes that have this in a real L2 configuration explicitly say so. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Initial SH-X3 SMP support.Paul Mundt2007-09-21
| | | | | | | | | | | This adds basic support for SH-X3 SMP (4 CPUs). More IPI and cache debugging is necessary, mostly interfacing the d-cache coherency and the I-cache broadcast invalidates. Only for testing at present! Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Hook up the SH-X3 SMP intc register groups.Magnus Damm2007-09-21
| | | | | Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Bring SMP support back from the dead.Paul Mundt2007-09-21
| | | | | | | | | | | There was a very preliminary bunch of SMP code scattered around for the SH7604 microcontrollers from way back when, and it has mostly suffered bitrot since then. With the tree already having been slowly getting prepped for SMP, this plugs in most of the remaining platform-independent bits. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: intc - initial SMP support.Magnus Damm2007-09-21
| | | | | | | | | | | | This implements initial support for the SMP INTC (particularly INTC2) controllers. These are largely implemented as conventional blocks, with register sets grouped together at fixed strides relative to the CPU id. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Wire up URAM node on SH7785.Paul Mundt2007-09-20
| | | | | | Add SH7785 URAM as node 1, follows the SH-X3 change. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: INTC stubs for SH7343 and SH7770 builds.Paul Mundt2007-09-20
| | | | | | | Get the SH7343 and SH7770 stuff linking again. Both of these still require proper INTC support. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: intc - irl mode update for sh7780 and sh7785Magnus Damm2007-09-20
| | | | | | | | | | | | | | This patch contains the following fixes and improvements: - Fix address typo for INTMSK2 / INTMSKCLR2 registers on sh7780. - Adds IRQ_MODE_IRLnnnn_MASK using intc controller for IRL masking. - Good old IRQ_MODE_IRLnnnn should not register any intc controller. - plat_irq_setup_pins() now selects IRL or IRQ mode. - the holding function is now disabled using ICR0. By default all external pin interrupts are disabled. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: remove CONFIG_CPU_HAS_INTC_IRQMagnus Damm2007-09-20
| | | | | | | | | All processor specific interrupt code is now converted to make use of the new intc code. The config option CONFIG_CPU_HAS_INTC_IRQ is because of that pointless. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Kill off volatile silliness in sq_flush_range().Paul Mundt2007-09-20
| | | | | | | | | | | CC arch/sh/kernel/cpu/sh4/sq.o arch/sh/kernel/cpu/sh4/sq.c: In function 'sq_flush_range': arch/sh/kernel/cpu/sh4/sq.c:65: warning: passing argument 1 of 'prefetch' discards qualifiers from pointer target type This didn't actually need to be volatile in the first place, so just kill off the qualifier entirely. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: intc - add support for sh7206Magnus Damm2007-09-20
| | | | | | | | | This patch converts the cpu specific interrupt setup code for sh7206 from ipr to intc. New vectors are also added to match the information provided by the datasheet. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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