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* sh: Mass ctrl_in/outX to __raw_read/writeX conversion.Paul Mundt2010-01-25
| | | | | | | | | | | The old ctrl in/out routines are non-portable and unsuitable for cross-platform use. While drivers/sh has already been sanitized, there is still quite a lot of code that is not. This converts the arch/sh/ bits over, which permits us to flag the routines as deprecated whilst still building with -Werror for the architecture code, and to ensure that future users are not added. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Replace an explicit computation by the use of the container_of macroNicolas Palix2009-12-08
| | | | | | | | | | | | | | | | | | | | | | The macro container_of from kernel.h performs the same pointer arithmetic operation. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ type T; expression mptr; expression member; @@ - (void *)((char *)mptr - offsetof(T, member)) + container_of(mptr, T, member) // </smpl> Signed-off-by: Nicolas Palix <npalix@diku.dk> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fixup last users of irq_chip->typenameThomas Gleixner2009-11-17
| | | | | | | | | The typename member of struct irq_chip was kept for migration purposes and is obsolete since more than 2 years. Fix up the leftovers. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: linux-sh@vger.kernel.org Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fixes some write posting issues in the interrupt handling for SHStuart Menefy2009-08-24
| | | | | | | | | | | It is possible for the CPU to re-enable it's interrupt block bit before the write to the interrupt controller has actually masked out the external interupt at the controller. We get around this by reading back from the interrupt controller which will ensure the write has happened. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Tie sparseirq in to Kconfig.Paul Mundt2009-06-11
| | | | | | | | | Now that the dependent patches are merged, we are ready to enable sparseirq support. This simply adds the Kconfig option, and then converts from the _cpu to the _node allocation routines to follow the upstream sparseirq API changes. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: irq: Fix up imask build warnings.Paul Mundt2009-05-26
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Wrap irq_to_desc_alloc_cpu() around CONFIG_SPARSE_IRQ temporarily.Paul Mundt2009-05-22
| | | | | | | | | irq_to_desc_alloc_cpu() has been renamed to irq_to_desc_alloc_node() in -next, but as we can not presently enable SPARSE_IRQ without the early irq_desc alloc patch, protect it with an ifdef until the interface has settled and we are ready to enable it system-wide. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: irq: Teach ipr and intc about dynamically allocating irq_descs.Paul Mundt2009-05-21
| | | | | | | | | | | | | | | | | This hooks in irq_to_desc_alloc_cpu() to the necessary code paths in the intc and ipr controller registration paths. As these are the primary call paths for all SH CPUs, this alone will make all CPUs sparse IRQ ready. There is the added benefit now that each CPU contains specific IPR and INTC tables, so only the vectors with interrupt sources backing them will ever see an irq_desc instantiation. This effectively packs irq_desc down to match the CPU, rather than padding NR_IRQS out to cover the valid vector range. Boards with extra sources will still have to fiddle with the nr_irqs setting, but they can continue doing so through the machvec as before. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: irq: Convert from irq_desc[] to irq_to_desc().Paul Mundt2009-05-21
| | | | | | | | This converts a few places that were using the old irq_desc[] array over to the shiny new irq_to_desc() helper. Preperatory work for sparse irq support. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: irq: Rework the SR.IMASK bitmap handling.Paul Mundt2009-05-21
| | | | | | | | This tidies up how the SR.IMASK bitmap is managed, using the bitmap API directly instead. At the same time, tidy up the irq_chip conversion a bit. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Kill off unused SH-5 irq_describe cruft.Paul Mundt2009-05-07
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Integrate the SH-5 onchip_remap() more coherently.Paul Mundt2009-05-07
| | | | | | | | | | | Presently this is special-cased for early initialization. While there are situations where these static early initializations are still necessary, with minor changes it is possible to use this for the regular ioremap implementation as well. This allows us to kill off the special-casing for the remap completely and to start tidying up all of the SH-5 special-casing in drivers. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: remove obsolete hw_interrupt_typeThomas Gleixner2009-05-03
| | | | | | | | | | Impact: cleanup Convert the last remaining users to struct irq_chip and remove the define. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Move the shared INTC code out to drivers/sh/Paul Mundt2008-10-01
| | | | | | | The INTC code will be re-used across different architectures, so move this out to drivers/sh/ and include/linux/sh_intc.h respectively. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Use __raw_xxx() I/O accessors for INTC and IPR.Paul Mundt2008-10-01
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: intc_prio_data() test before subtraction on unsignedroel kluin2008-09-09
| | | | | | | bit is unsigned, so test before subtraction Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: migrate to arch/sh/include/Paul Mundt2008-07-28
| | | | | | | | | | | | | This follows the sparc changes a439fe51a1f8eb087c22dd24d69cebae4a3addac. Most of the moving about was done with Sam's directions at: http://marc.info/?l=linux-sh&m=121724823706062&w=2 with subsequent hacking and fixups entirely my fault. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: add interrupt ack code to sh4aYoshihiro Shimoda2008-07-28
| | | | | | | | This patch is based on interrupt acknowledge code for external interrupt sources on sh3 processors and adds on sh4a processors. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh/kernel/cpu/irq/intc-sh5.c build fixAdrian Bunk2008-06-01
| | | | | | | | | | | | | | | | | | | | This patch fixes the following build error caused by commit a1dc4b59fa4af97ae68ee214d4d72bbd7c7ec1dc (sh: intc_sh5 depends on cayman board for IRQ priority table.): <-- snip --> ... CC arch/sh/kernel/cpu/irq/intc-sh5.o /home/bunk/linux/kernel-2.6/git/linux-2.6/arch/sh/kernel/cpu/irq/intc-sh5.c: In function 'plat_irq_setup': /home/bunk/linux/kernel-2.6/git/linux-2.6/arch/sh/kernel/cpu/irq/intc-sh5.c:257: error: expected declaration or statement at end of input make[4]: *** [arch/sh/kernel/cpu/irq/intc-sh5.o] Error 1 <-- snip --> Reported-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: intc register modify fixMagnus Damm2008-05-08
| | | | | | | | Make sure register modifications stay atomic. Fixes processors with shared priority register masking. Dual bitmap masking is unaffected. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: no high level trigger on some sh3 cpusMagnus Damm2008-05-08
| | | | | | | | | The processor models sh7706, sh7707 and sh7709 don't support high level trigger sense configuration. And the intc code looks like crap these days so what's the difference. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: add interrupt ack code to sh3Magnus Damm2008-05-08
| | | | | | | | | This patch adds interrupt acknowledge code for external interrupt sources on sh3 processors. Only really required for edge triggered interrupts, but we ack regardless of sense configuration. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: intc_sh5 depends on cayman board for IRQ priority table.Paul Mundt2008-05-08
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Shut up some trivial build warnings.Paul Mundt2008-02-14
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: remove maskreg irq codeMagnus Damm2008-02-14
| | | | | | | This patch removes the maskreg irq code since it is not in use anymore. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: intc - remove default interrupt priority tablesMagnus Damm2008-01-27
| | | | | | | | | | | | | This patch removes interrupt priority tables from the intc code. Optimal priority assignment varies with embedded application anyway, so keeping the interrupt priority tables together with cpu-specific code doesn't make sense. The function intc_set_priority() should be used instead to set the desired interrupt priority level. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: comment tidying for sh64->sh migration.Paul Mundt2008-01-27
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Get the mach-cayman IRQ support building.Paul Mundt2008-01-27
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: imask IRQ depends on sh32.Paul Mundt2008-01-27
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Kill off dead ipr_irq_demux().Paul Mundt2007-10-31
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: intc - initial SMP support.Magnus Damm2007-09-21
| | | | | | | | | | | | This implements initial support for the SMP INTC (particularly INTC2) controllers. These are largely implemented as conventional blocks, with register sets grouped together at fixed strides relative to the CPU id. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: remove CONFIG_CPU_HAS_INTC_IRQMagnus Damm2007-09-20
| | | | | | | | | All processor specific interrupt code is now converted to make use of the new intc code. The config option CONFIG_CPU_HAS_INTC_IRQ is because of that pointless. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: intc - primary priority masking fixesMagnus Damm2007-09-20
| | | | | | | | | | | | | | | | | | | | This patch contains various intc fixes for problems reported by Markus Brunner on the linuxsh-dev mailing list: http://marc.info/?l=linuxsh-dev&m=118701948224991&w=1 Apart from added comments, the fixes are: - add intc_set_priority() function prototype to hw_irq.h - fix off-by-one error in intc_set_priority() - make sure _INTC_WIDTH() is set for primary priority masking Big thanks to Markus for finding these problems. Version two fixes a compile error and an inverted primary check. Signed-off-by: Magnus Damm <damm@igel.co.jp> Acked-by: Markus Brunner <super.firetwister@gmail.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: intc - rework core codeMagnus Damm2007-09-20
| | | | | | | | | | | | | | | | | This patch reworks the intc core, implementing the following features: - Support dual priority registers - one set and one clear register - All 8/16/32 bit register combinations are now supported - Both single mask and single enable bitmap register are supported - Add code to set interrupt priority - Speedup sense and priority configuration code - Allocate data using bootmem, allows intc data structures to be __initdata - Save memory - allocated memory footprint is smaller than intc structures Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: intc - add a clear register to struct intc_prio_regMagnus Damm2007-09-20
| | | | | | | | We need a secondary register member in struct intc_prio_reg to support dual priority registers used by ipi on x3. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: intc: Fix sense regs oops for IRL IRQs.Paul Mundt2007-09-20
| | | | | | | | IRL doesn't always define sense registers, so don't bother trying to iterate through the table. This ended up causing an oops on SH-X3 when using IRL mode. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: remove intc2 codeMagnus Damm2007-09-20
| | | | | | | There is no point in keeping around the now unused intc2 code. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: intc - add single bitmap register supportMagnus Damm2007-09-20
| | | | | | | | | | | | This patch adds single bitmap register support to intc. The current code only handles 16 and 32 bit registers where a set bit means interrupt enabled, but this is easy to extend in the future. The INTC_IRQ() macro is also added to provide a way to hook in interrupt controllers for FPGAs in boards or companion chips. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: remove support for sh7300 and solution engine 7300Magnus Damm2007-07-26
| | | | | | | | | This patch removes old dead code: - kill off sh7300 cpu support - get rid of broken solution engine 7300 board support Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: remove old broken pint codeMagnus Damm2007-07-24
| | | | | | | | | The code in arch/sh/kernel/cpu/irq/pint.c doesn't compile, so let's get rid of it to make space for a future pint implementation on top of intc. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: intc - improve group supportMagnus Damm2007-07-19
| | | | | | | | | | | | | This patch improves intc group support, ie it makes it possible to group interrupts together and mask / unmask the entire group. This also works with priorities, so setting a priority for an entire group is also possible. This patch is needed to properly support certain processors such as the 7780. Fixes for NULL pointers in DECLARE_INTC_DESC() are also included. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: intc - shared IPR and INTC2 controllerMagnus Damm2007-07-19
| | | | | | | | | | | | | | | | | | | | | | | This is the second version of the shared interrupt controller patch for the sh architecture, fixing up handling of intc_reg_fns[]. The three main advantages with this controller over the existing ones are: - Both priority (ipr) and bitmap (intc2) registers are supported - External pin sense configuration is supported, ie edge vs level triggered - CPU/Board specific code maps 1:1 with datasheet for easy verification This controller can easily coexist with the current IPR and INTC2 controllers, but the idea is that CPUs/Boards should be moved over to this controller over time so we have a single code base to maintain. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Hook up hard_smp_processor_id() for INTC2 block.Paul Mundt2007-06-20
| | | | | | | We need to know the CPU ID in order to calculate the mask and ack registers effectively. Stub this in for UP. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: rework ipr codeMagnus Damm2007-06-15
| | | | | | | | | | | | | | | | | This patch reworks the ipr code by grouping the offset array together with the ipr_data structure in a new data structure called ipr_desc. This new structure also contains the name of the controller in struct irq_chip. The idea behind putting struct irq_chip in there is that we can use offsetof() to locate the base addresses in the irq_chip callbacks. This strategy has much in common with the recently merged intc2 code. One logic change has been made - the original ipr code enabled the interrupts by default but with this patch they are all disabled by default. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: rework intc2 codeMagnus Damm2007-06-14
| | | | | | | | | | | | | | | | | | | The shared intc2 code currently contains cpu-specific #ifdefs. This is a tad unclean and it prevents us from using the shared code to drive board-specific irqs on the se7780 board. This patch reworks the intc2 code by moving the base addresses of the intc2 registers into struct intc2_desc. This new structure also contains the name of the controller in struct irq_chip. The idea behind putting struct irq_chip in there is that we can use offsetof() to locate the base addresses in the irq_chip callbacks. One logic change has been made - the original shared intc2 code enabled the interrupts by default but with this patch they are all disabled by default. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* spelling fixes: arch/sh/Simon Arlott2007-05-21
| | | | | | | Spelling fixes in arch/sh/. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Solution Engine SH7705 board and CPU updates.Nobuhiro Iwamatsu2007-05-06
| | | | | | | | This fixes up SH7705 CPU support and the SE7705 board for some of the recent changes. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.zh@hitachi.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Add SH7785 Highlander board support (R7785RP).Paul Mundt2007-05-06
| | | | | | | | | | | This adds preliminary support for the SH7785-based Highlander board. Some of the Highlander support code is reordered so that most of it can be reused directly. This also plugs in missing SH7785 checks in the places that need it, as this is the first board to support the CPU. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: shmin updates.Takashi YOSHII2007-02-12
| | | | | | | | This fixes up shmin (and SH7706/SH7708) IPR support for some of the recent API changes. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: sh775x/titan fixes for irq header changes.Jamie Lenehan2006-12-05
| | | | | | | | | | | | | | | | | | | | | The following moves the creation of IPR interupts into setup-7750.c and updates a few other things to make it all work after the "Drop CPU subtype IRQ headers" commit. It boots and runs fine on my titan board. - adds an ipr_idx to the ipr_data and uses a function in the subtype code to calculate the address of the IPR registers - adds a function to enable individual interrupt mode for externals in the subtype code and calls that from the titan board code instead of doing it directly. - I changed the shift in the ipr_data to be the actual # of bits to shift, instead of the numnber / 4 - made it easier to match with the manual. Signed-off-by: Jamie Lenehan <lenehan@twibble.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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