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* sh: Flush ITLB too in PTEAEX's flush_tlb_page()Matt Fleming2010-03-23
| | | | | | | | | flush_tlb_page() can be used to flush TLB entries that map executable pages. Therefore, we need to ensure that the ITLB is also flushed in local_flush_tlb_page(). Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Add watch-dog register address for SH7722/SH7723/SH7724Kuninori Morimoto2010-03-23
| | | | | Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: merge sh7722 and sh7724 DMA register definitionsGuennadi Liakhovetski2010-03-01
| | | | | | | DMA CHCR register layout is equal on sh7722 and sh7724, reuse definitions. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* dmaengine: shdma: separate DMA headers.Guennadi Liakhovetski2010-03-01
| | | | | | | | | | Separate SH DMA headers into ones, commonly used by both drivers, and ones, specific to each of them. This will make the future development of the dmaengine driver easier. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fix up more 64-bit pgprot truncation on SH-X2 TLB.Paul Mundt2010-02-16
| | | | | | | | | | | Both the store queue API and the PMB remapping take unsigned long for their pgprot flags, which cuts off the extended protection bits. In the case of the PMB this isn't really a problem since the cache attribute bits that we care about are all in the lower 32-bits, but we do it just to be safe. The store queue remapping on the other hand depends on the extended prot bits for enabling userspace access to the mappings. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* Merge branch 'sh/dmaengine'Paul Mundt2010-02-07
|\ | | | | | | | | Conflicts: arch/sh/drivers/dma/dma-sh.c
| * sh: implement DMA_SLAVE capability in SH dmaengine driverGuennadi Liakhovetski2010-02-07
| | | | | | | | | | | | | | | | Tested to work with a SIU ASoC driver on sh7722 (migor). Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: fix Transfer Size calculation in both DMA driversGuennadi Liakhovetski2010-02-07
| | | | | | | | | | | | | | | | | | | | | | | | | | Both the original arch/sh/drivers/dma/dma-sh.c and the new SH dmaengine drivers do not take into account bits 3:2 of the Transfer Size field in the CHCR register, besides, bit-field defines set bit 2, but the mask only passes bits 1:0 through. TS_16BLK and TS_32BLK macros are bogus too. This patch fixes all these issues for sh7722 and sh7724, other CPUs stay unchanged and might need to be fixed too. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | sh: mach-sdk7786: Probe system FPGA area mapping.Paul Mundt2010-01-20
| | | | | | | | | | | | | | | | | | | | | | | | | | This implements dynamic probing for the system FPGA. The system reset controller contains a fixed magic read word in order to identify the FPGA. This just utilizes a simple loop that scans across all of the fixed physical areas (area 0 through area 6) to locate the FPGA. The FPGA also contains register information detailing the area mappings and chip select settings for all of the other blocks, so this needs to be done before we can set up anything else. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | sh: New extended page flag to wire/unwire TLB entriesMatt Fleming2010-01-16
| | | | | | | | | | | | | | | | Provide a new extended page flag, _PAGE_WIRED and an SH4 implementation for wiring TLB entries and use it in the fixmap code path so that we can wire the fixmap TLB entry. Signed-off-by: Matt Fleming <matt@console-pimps.org>
* | sh: Kill off dead UBC headers.Paul Mundt2010-01-05
|/ | | | | | Nothing is using these now, so kill them all off. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: dmaengine support for sh7724.Guennadi Liakhovetski2009-12-17
| | | | | | | | Add a dmaengine platform device to sh7724, fix DMA channel interrupt numbers. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: fix watchdog timer for sh7780/sh7785Valentin R Sitsikov2009-10-26
| | | | | Signed-off-by: Valentin Sitdikov <valentin.sitdikov@siemens.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* Merge branch 'master' into sh/smpPaul Mundt2009-09-01
|\ | | | | | | | | Conflicts: arch/sh/mm/cache-sh4.c
| * sh: Add initial support for SH7757 CPU subtypeYoshihiro Shimoda2009-08-21
| | | | | | | | | | Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | sh: Migrate SH-4 cacheflush ops to function pointers.Paul Mundt2009-08-14
| | | | | | | | | | | | | | | | | | | | This paves the way for allowing individual CPUs to overload the individual flushing routines that they care about without having to depend on weak aliases. SH-4 is converted over initially, as it wires up pretty much everything. The majority of the other CPUs will simply use the default no-op implementation with their own region flushers wired up. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | sh: Kill off unused flush_icache_user_range().Paul Mundt2009-08-14
| | | | | | | | | | | | | | | | We use flush_cache_page() outright in copy_to_user_page(), and nothing else needs it, so just kill it off. SH-5 still defines its own version, but that too will go away in the same fashion once it converts over. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | sh: consolidate flush_dcache_mmap_lock/unlock() definitions.Paul Mundt2009-08-14
| | | | | | | | | | | | | | | | All of the flush_dcache_mmap_lock()/flush_dcache_mmap_unlock() definitions are identical across all CPUs, so just provide them generically in asm/cacheflush.h. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | sh: Don't export flush_dcache_all().Paul Mundt2009-08-14
| | | | | | | | | | | | | | flush_dcache_all() is used internally by the SH-4 cache code, it is not part of the exported cache API, so make it static and don't export it. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | sh: Centralize the CPU cache initialization routines.Paul Mundt2009-08-14
| | | | | | | | | | | | | | | | This provides a central point for CPU cache initialization routines. This replaces the antiquated p3_cache_init() method, which the vast majority of CPUs never cared about. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | sh: rework nommu for generic cache.c use.Paul Mundt2009-08-14
| | | | | | | | | | | | | | This does a bit of reorganizing for allowing nommu to use the new and generic cache.c, no functional changes. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | Merge branch 'master' into sh/cachetlbPaul Mundt2009-08-14
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| * sh: Add SH7724 DMAC support.Kuninori Morimoto2009-08-04
| | | | | | | | | | Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * sh: hwblk support for sh7724Magnus Damm2009-08-04
| | | | | | | | | | | | | | This patch adds hwblk support for the sh7724 processor. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | sh: Migrate from PG_mapped to PG_dcache_dirty.Paul Mundt2009-07-22
|/ | | | | | | | | | | | | | | | | This inverts the delayed dcache flush a bit to be more in line with other platforms. At the same time this also gives us the ability to do some more optimizations and cleanup. Now that the update_mmu_cache() callsite only tests for the bit, the implementation can gradually be split out and made generic, rather than relying on special implementations for each of the peculiar CPU types. SH7705 in 32kB mode and SH-4 still need slightly different handling, but this is something that can remain isolated in the varying page copy/clear routines. On top of that, SH-X3 is dcache coherent, so there is no need to bother with any of these tests in the PTEAEX version of update_mmu_cache(), so we kill that off too. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: hwblk support for sh7723Magnus Damm2009-07-19
| | | | | | | This patch adds hwblk support for the sh7723 processor. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: hwblk for sh7722Magnus Damm2009-07-04
| | | | | | | | | | | | This patch contains the sh7722 specific hwblk implementation. Hwblk ids are added to the processor specific header file, module stop bits and areas are kept track of as hwblks, clocks are converted to make use of the shared hwblk code. Code to determine allowed sleep modes is also added. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: sh7722 mode pin definitionsMagnus Damm2009-06-11
| | | | | | | | This patch adds sh7722 mode pin and pin function controller comments. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: sh7724 mode pin commentsMagnus Damm2009-06-11
| | | | | | | | This patch adds comments for the sh7724 mode pins and pin function controller. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: sh7723 mode pin V2Magnus Damm2009-06-11
| | | | | | | | This patch is sh7723 mode pin V2. Mode pins and pin function controller comments are added. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: rework mode pin codeMagnus Damm2009-06-11
| | | | | | | | | | | | | This patch reworks the mode pin code to keep the pin definitions in one place. The mode pins values are now the value of the bit instead of bit number. With this patch in place the sh7785 header file contains mode pin comments. The sh7785 clock code and the sh7785lcr board code are updated to reflect the new shared mode pins. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: add RAMCR definition for sh4Kuninori Morimoto2009-06-01
| | | | | Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: sh7785 mode pin definitionsMagnus Damm2009-06-01
| | | | | | | | This patch adds sh7785 mode pin definitions. Mode pins and pin function controller comments are added as well. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: remove old TMU driverMagnus Damm2009-05-12
| | | | | | | | | | | | | | | | | This patch removes the old TMU driver (CONFIG_SH_TMU/timer-tmu.c) As replacement, select the sh_tmu driver with CONFIG_SH_TIMER_TMU and configure timer channel using platform data. If multiple TMU channels are enabled using platform data, use the earlytimer parameter on the kernel command line to select channel. For instance, use "earlytimer=sh_tmu.0" to select the first channel. To verify which timer is being used, look at printouts or the timer irq count in /proc/interrupts. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Add support for SH7724 (SH-Mobile R2R) CPU subtype.Kuninori Morimoto2009-04-16
| | | | | | | | This implements initial support for the SH-Mobile R2R CPU. Based on Rev 0.11 of the initial SH7724 hardware manual. Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Tidy up sh7786 pinmux table.Kuninori Morimoto2009-03-30
| | | | | | | Formatting and typo fix. Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Support for extended ASIDs on PTEAEX-capable SH-X3 cores.Paul Mundt2009-03-17
| | | | | | | | | | | | | | | | | | | | This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores that implement the PTAEX register and respective functionality. Presently only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs). The main change is in how the PTE is written out when loading the entry in to the TLB, as well as in how the TLB entry is selectively flushed. While SH-X2 extended mode splits out the memory-mapped U and I-TLB data arrays for extra bits, extended ASID mode splits out the address arrays. While we don't use the memory-mapped data array access, the address array accesses are necessary for selective TLB flushes, so these are implemented newly and replace the generic SH-4 implementation. With this, TLB flushes in switch_mm() are almost non-existent on newer parts. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: dma-sh updates for multi IRQ and new SH-4A CPUs.Nobuhiro Iwamatsu2009-03-10
| | | | | | | | | | | This adds DMA support for newer SH-4A CPUs, particularly SH7763/64/80/85. This also enables multi IRQ support for platforms that have multiple vectors bound to the same IRQ source. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Add support for SH7786 CPU subtype.Kuninori Morimoto2009-03-03
| | | | | | | | | | | | | | This adds preliminary support for the SH7786 CPU subtype. While this is a dual-core CPU, only UP is supported for now. L2 cache support is likewise not yet implemented. More information on this particular CPU subtype is available at: http://www.renesas.com/fmwk.jsp?cnt=sh7786_root.jsp&fp=/products/mpumcu/superh_family/sh7780_series/sh7786_group/ Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Add on-chip RTC support for SH7722.Paul Mundt2008-10-28
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: sh7785 pinmux supportMagnus Damm2008-10-22
| | | | | | | This patch implements pinmux tables for the sh7785 processor. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Move SH-4 CPU headers down one more level.Paul Mundt2008-10-20
| | | | | | | These accidentally got placed in to cpu-sh4 instead of cpu-sh4/cpu, push them down one more level. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: migrate to arch/sh/include/Paul Mundt2008-07-28
This follows the sparc changes a439fe51a1f8eb087c22dd24d69cebae4a3addac. Most of the moving about was done with Sam's directions at: http://marc.info/?l=linux-sh&m=121724823706062&w=2 with subsequent hacking and fixups entirely my fault. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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