| Commit message (Collapse) | Author | Age | |
|---|---|---|---|
| * | s390/mm,tlb: correct tlb flush on page table upgrade | Martin Schwidefsky | 2013-11-04 |
| | | | | | | | | | | | | | The IDTE instruction used to flush TLB entries for a specific address space uses the address-space-control element (ASCE) to identify affected TLB entries. The upgrade of a page table adds a new top level page table which changes the ASCE. The TLB entries associated with the old ASCE need to be flushed and the ASCE for the address space needs to be replaced synchronously on all CPUs which currently use it. The concept of a lazy ASCE update with an exception handler is broken. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com> | ||
| * | s390/traps: preinitialize program check table | Heiko Carstens | 2012-11-23 |
| Preinitialize the program check table, so we can put it into the read-only data section. Also use only four byte entries for the table, since each program check handler resides within the first 2GB. Therefore this reduces the size of the table by 50% on 64 bit builds. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com> | |||
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index : litmus-rt.git | |
| The LITMUS^RT kernel. | Bjoern Brandenburg |
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