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| * powerpc/powernv: Set memory_block_size_bytes to 256MBAnton Blanchard2014-06-04
| | | | | | | | | | | | | | | | | | | | | | powerpc sets a low SECTION_SIZE_BITS to accomodate small pseries boxes. We default to 16MB memory blocks, and boxes with a lot of memory end up with enormous numbers of sysfs memory nodes. Set a more reasonable default for powernv of 256MB. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * powerpc: Allow ppc_md platform hook to override memory_block_size_bytesAnton Blanchard2014-06-04
| | | | | | | | | | | | | | | | | | | | | | The pseries platform code unconditionally overrides memory_block_size_bytes regardless of the running platform. Create a ppc_md hook that so each platform can choose to do what it wants. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * powerpc/powernv: Fix endian issues in memory error handling codeAnton Blanchard2014-06-04
| | | | | | | | | | | | | | | | struct OpalMemoryErrorData is passed to us from firmware, so we have to byteswap it. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * powerpc/powernv: Provide debugfs access to the LPC bus via OPALBenjamin Herrenschmidt2014-06-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This provides debugfs files to access the LPC bus on Power8 non-virtualized using the appropriate OPAL firmware calls. The usage is simple: one file per space (IO, MEM and FW), lseek to the address and read/write the data. IO and MEM always generate series of byte accesses. FW can generate word and dword accesses if aligned properly. Based on an original patch from Rob Lippert and reworked. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * powerpc/powernv: Add calls to support little endian hostBenjamin Herrenschmidt2014-06-04
| | | | | | | | | | | | | | | | | | | | | | | | | | When running as a powernv "host" system on P8, we need to switch the endianness of interrupt handlers. This does it via the appropriate call to the OPAL firmware which may result in just switching HID0:HILE but depending on the processor version might need to do a few more things. This call must be done early before any other processor has been brought out of firmware. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Andy Whitcroft <apw@canonical.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * powerpc/powernv: Add support for POWER8 split core on powernvMichael Ellerman2014-05-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upcoming POWER8 chips support a concept called split core. This is where the core can be split into subcores that although not full cores, are able to appear as full cores to a guest. The splitting & unsplitting procedure is mildly complicated, and explained at length in the comments within the patch. One notable detail is that when splitting or unsplitting we need to pull offline cpus out of their offline state to do work as part of the procedure. The interface for changing the split mode is via a sysfs file, eg: $ echo 2 > /sys/devices/system/cpu/subcores_per_core Currently supported values are '1', '2' and '4'. And indicate respectively that the core should be unsplit, split in half, and split in quarters. These modes correspond to threads_per_subcore of 8, 4 and 2. We do not allow changing the split mode while KVM VMs are active. This is to prevent the value changing while userspace is configuring the VM, and also to prevent the mode being changed in such a way that existing guests are unable to be run. CPU hotplug fixes by Srivatsa. max_cpus fixes by Mahesh. cpuset fixes by benh. Fix for irq race by paulus. The rest by mikey and mpe. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com> Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * powerpc/powernv: Make it possible to skip the IRQHAPPENED check in power7_nap()Michael Ellerman2014-05-27
| | | | | | | | | | | | | | | | | | | | | | | | | | To support split core we need to be able to force all secondaries into nap, so the core can detect they are idle and do an unsplit. Currently power7_nap() will return without napping if there is an irq pending. We want to ignore the pending irq and nap anyway, we will deal with the interrupt later. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * Merge remote-tracking branch 'scott/next' into nextBenjamin Herrenschmidt2014-05-27
| |\ | | | | | | | | | | | | | | | | | | | | | << Highlights include a few new boards, a device tree binding for CCF (including backwards-compatible device tree updates to distinguish incompatible versions), and some fixes. >>
| | * powerpc/mpc85xx: Add BSC9132 QDS Supportharninder rai2014-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - BSC9132 is an integrated device that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 technologies with MAPLE-B2F baseband acceleration processing elements - BSC9132QDS Overview 2Gbyte DDR3 (on board DDR) 32Mbyte 16bit NOR flash 128Mbyte 2K page size NAND Flash 256 Kbit M24256 I2C EEPROM 128 Mbit SPI Flash memory SD slot eTSEC1: Connected to SGMII PHY eTSEC2: Connected to SGMII PHY DUART interface: supports one UARTs up to 115200 bps for console display Signed-off-by: Harninder Rai <harninder.rai@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| | * powerpc/mpc85xx: Remove P1023 RDS supportLijun Pan2014-05-22
| | | | | | | | | | | | | | | | | | | | | P1023RDS is no longer supported/manufactured by Freescale while P1023RDB is. Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| | * powerpc/fsl-booke: Add initial T104x_QDS board supportPrabhakar Kushwaha2014-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for T104x board in board file t104x_qds.c, It is common for both T1040 and T1042 as they share same QDS board. T1040QDS board Overview ----------------------- - SERDES Connections, 8 lanes supporting: — PCI Express: supporting Gen 1 and Gen 2; — SGMII — QSGMII — SATA 2.0 — Aurora debug with dedicated connectors (T1040 only) - DDR Controller - Supports rates of up to 1600 MHz data-rate - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types. -IFC/Local Bus - NAND flash: 8-bit, async, up to 2GB. - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB - GASIC: Simple (minimal) target within Qixis FPGA - PromJET rapid memory download support - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep (T1040 only) - QIXIS System Logic FPGA - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - Video - DIU supports video at up to 1280x1024x32bpp - USB - Supports two USB 2.0 ports with integrated PHYs — Two type A ports with 5V@1.5A per port. — Second port can be converted to OTG mini-AB - SDHC - SDHC port connects directly to an adapter card slot, featuring: - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC — Supporting eMMC memory devices - SPI - On-board support of 3 different devices and sizes - Other IO - Two Serial ports - ProfiBus port - Four I2C ports Add T104xQDS support in Kconfig and Makefile. Also create device tree. Following features are currently not implmented. - SerDes: Aurora - IFC: GASIC, Promjet - QIXIS - Ethernet - DIU - power supplies management - ProfiBus Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| | * powerpc/85xx: Add OCA4080 board supportMartijn de Gouw2014-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OCA4080 overview: - 1.466 GHz Freescale QorIQ P4080E Processor - 4Gbyte DDR3 on board - 8Mbyte Nor flash - Serial RapidIO 1.2 - 1 x 10/100/1000 BASE-T front ethernet - 1 x 1000 BASE-BX ethernet on AMC connector Signed-off-by: Martijn de Gouw <martijn.de.gouw@prodrive.nl> [scottwood@freescale.com: minor conflict-related changes] Signed-off-by: Scott Wood <scottwood@freescale.com>
| | * powerpc/mpc85xx: add support for Keymile's kmcoge4 boardValentin Longchamp2014-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces the support for Keymile's kmcoge4 board which is the internal reference design for boards based on Freescale's P2040/P2041 SoCs. This internal reference design is named kmp204x. The peripherals used on this board are: - SPI NOR Flash as bootloader medium - NAND Flash with a ubi partition - 2 PCIe busses (hosts 1 and 3) - 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5) - 4 Local Bus windows, with one dedicated to the QRIO reset/power mgmt CPLD - 2 I2C busses - last but not least, the mandatory serial port The patch also adds a defconfig file for this reference design that is necessary because of the lowmem option that must be set higher due to the number of PCIe devices with big ioremapped mem ranges on the boad. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | Revert "powerpc/powernv: Fundamental reset on PLX ports"Benjamin Herrenschmidt2014-05-19
| |/ | | | | | | | | | | | | | | | | | | This reverts commit b2b5efcf208ddc9444aca77336627428782a39f4. This code was way too board specific, there are quirks as to how the PERST line is wired on different boards, we'll have to revisit this using/creating appropriate firmware interfaces. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * Merge remote-tracking branch 'anton/abiv2' into nextBenjamin Herrenschmidt2014-05-05
| |\ | | | | | | | | | | | | | | | | | | This series adds support for building the powerpc 64-bit LE kernel using the new ABI v2. We already supported running ABI v2 userspace programs but this adds support for building the kernel itself using the new ABI.
| | * powerpc: Fix SMP issues with ppc64le ABIv2Anton Blanchard2014-04-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to put a function descriptor in __secondary_hold_spinloop. Use ppc_function_entry to get the instruction address and put it in __secondary_hold_spinloop instead. Also fix an issue where we assumed cur_cpu_spec held a function descriptor. Signed-off-by: Anton Blanchard <anton@samba.org>
| | * powerpc: Fix unsafe accesses to parameter area in ELFv2Ulrich Weigand2014-04-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the assembler files in lib/ make use of the fact that in the ELFv1 ABI, the caller guarantees to provide stack space to save the parameter registers r3 ... r10. This guarantee is no longer present in ELFv2 for functions that have no variable argument list and no more than 8 arguments. Change the affected routines to temporarily store registers in the red zone and/or the top of their own stack frame (in the space provided to save r31 .. r29, which is actually not used in these routines). In opal_query_takeover, simply always allocate a stack frame; the routine is not performance critical. Signed-off-by: Ulrich Weigand <ulrich.weigand@de.ibm.com> Signed-off-by: Anton Blanchard <anton@samba.org>
| | * powerpc: Remove superflous function descriptors in assembly only codeAnton Blanchard2014-04-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have a number of places where we load the text address of a local function and indirectly branch to it in assembly. Since it is an indirect branch binutils will not know to use the function text address, so that trick wont work. There is no need for these functions to have a function descriptor so we can replace it with a label and remove the dot symbol. Signed-off-by: Anton Blanchard <anton@samba.org>
| | * powerpc: No need to use dot symbols when branching to a functionAnton Blanchard2014-04-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | binutils is smart enough to know that a branch to a function descriptor is actually a branch to the functions text address. Alan tells me that binutils has been doing this for 9 years. Signed-off-by: Anton Blanchard <anton@samba.org>
| * | ppc476: Enable a linker work around for IBM errata #46Alistair Popple2014-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds an option to enable a work around for an icache bug on 476 that can cause execution of stale instructions when falling through pages (IBM errata #46). It requires a recent version of binutils which supports the --ppc476-workaround option. The work around enables the appropriate linker options and ensures that all module output sections are aligned to 4K page boundaries. The work around is only required when building modules. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc: Added PCI MSI support using the HSTA moduleAlistair Popple2014-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PPC476GTR SoC supports message signalled interrupts (MSI) by writing to special addresses within the High Speed Transfer Assist (HSTA) module. This patch adds support for PCI MSI with a new system device. The DMA window is also updated to allow access to the entire 42-bit address range to allow PCI devices write access to the HSTA module. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | IBM Akebono: Add the Akebono platformAlistair Popple2014-04-30
| | | | | | | | | | | | | | | | | | | | | This patch adds support for the IBM Akebono board. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | IBM Currituck: Clean up board specific code before adding Akebono codeAlistair Popple2014-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IBM Akebono code uses the same initialisation functions as the earlier Currituck board. Rather than create a copy of this code for Akebono we will instead integrate support for it into the same file as the Currituck code. This patch just renames the board support file and updates the Makefile. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc/le: Show the endianess of the LPAR under PowerVM.Tony Breeds2014-04-30
| | | | | | | | | | | | | | | Signed-off-by: Tony Breeds <tony@bakeyournoodle.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc: powernv: Implement ppc_md.get_proc_freq()Gautham R. Shenoy2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement a method named pnv_get_proc_freq(unsigned int cpu) which returns the current clock rate on the 'cpu' in Hz to be reported in /proc/cpuinfo. This method uses the value reported by cpufreq when such a value is sane. Otherwise it falls back to old way of reporting the clockrate, i.e. ppc_proc_freq. Set the ppc_md.get_proc_freq() hook to pnv_get_proc_freq() on the PowerNV platform. Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc/powernv: Return secondary CPUs to firmware before FW updateVasant Hegde2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Firmware update on PowerNV platform takes several minutes. During this time one CPU is stuck in FW and the kernel complains about "soft lockups". This patch returns all secondary CPUs to firmware before starting firmware update process. [ Reworked a bit and cleaned up -- BenH ] Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc/legacy_serial: Support MVME5100 UARTS with shifted registersStephen Chivers2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support to legacy serial for UARTS with shifted registers. The MVME5100 Single Board Computer is a PowerPC platform that has 16550 style UARTS with register addresses that are 16 bytes apart (shifted by 4). Commit 309257484cc1a592e8ac5fbdd8cd661be2b80bf8 "powerpc: Cleanup udbg_16550 and add support for LPC PIO-only UARTs" added support to udbg_16550 for shifted registers by adding a "stride" parameter to the initialisation operations for Programmed IO and Memory Mapped IO. As a consequence it is now possible to use the services of legacy serial to provide early serial console messages for the MVME5100. An added benefit of this is that the serial console will always be "ttyS0" irrespective of whether the computer is fitted with extra PCI 8250 interface boards or not. I have tested this patch using the four PowerPC platforms available to me: MVME5100 - shifted registers, SAM440EP - unshifted registers, MPC8349 - unshifted registers, MVME4100 - unshifted registers. Signed-off-by: Stephen Chivers <schivers@csc.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc/boot: Add support for 64bit little endian wrapperCédric Le Goater2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code is only slightly modified : entry points now use the FIXUP_ENDIAN trampoline to switch endian order. The 32bit wrapper is kept for big endian kernels and 64bit is enforced for little endian kernels with a PPC64_BOOT_WRAPPER config option. The linker script is generated using the kernel preprocessor flags to make use of the CONFIG_* definitions and the wrapper script is modified to take into account the new elf64ppc format. Finally, the zImage file is compiled as a position independent executable (-pie) which makes it loadable at any address by the firmware. Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc/powernv: Don't use pe->pbus to get the domain numberGavin Shan2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the PE contains single PCI function, "pe->pbus" would be NULL. It's not reliable to be used by pci_domain_nr(). We just grab the PCI domain number from the PCI host controller (struct pci_controller) instance. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc/powernv: Missed IOMMU table typeGavin Shan2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In function pnv_pci_ioda2_setup_dma_pe(), the IOMMU table type is set to (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE) unconditionally. It was just set to TCE_PCI by pnv_pci_setup_iommu_table(). So the primary IOMMU table type (TCE_PCI) is lost. The patch fixes it. Also, pnv_pci_setup_iommu_table() already set "tbl->it_busno" to zero and we needn't do it again. The patch removes the redundant assignment. The patch also fixes similar issues in pnv_pci_ioda_setup_dma_pe(). Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc/powernv: Fundamental reset on PLX portsGavin Shan2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch intends to support fundamental reset on PLX downstream ports. If the PCI device matches any one of the internal table, which includes PLX vendor ID, bridge device ID, register offset for fundamental reset and bit, fundamental reset will be done accordingly. Otherwise, it will fail back to hot reset. Additional flag (EEH_DEV_FRESET) is introduced to record the last reset type on the PCI bridge. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powrpc/powernv: Reset PHB in kdump kernelGavin Shan2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the kdump scenario, the first kerenl doesn't shutdown PCI devices and the kdump kerenl clean PHB IODA table at the early probe time. That means the kdump kerenl can't support PCI transactions piled by the first kerenl. Otherwise, lots of EEH errors and frozen PEs will be detected. In order to avoid the EEH errors, the PHB is resetted to drop all PCI transaction from the first kerenl. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc/pci: Mask linkDown on resetting PCI busGavin Shan2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The problem was initially reported by Wendy who tried pass through IPR adapter, which was connected to PHB root port directly, to KVM based guest. When doing that, pci_reset_bridge_secondary_bus() was called by VFIO driver and linkDown was detected by the root port. That caused all PEs to be frozen. The patch fixes the issue by routing the reset for the secondary bus of root port to underly firmware. For that, one more weak function pci_reset_secondary_bus() is introduced so that the individual platforms can override that and do specific reset for bridge's secondary bus. Reported-by: Wendy Xiong <wenxiong@linux.vnet.ibm.com> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc/eeh: Make the delay for PE reset unifiedGavin Shan2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Basically, we have 3 types of resets to fulfil PE reset: fundamental, hot and PHB reset. For the later 2 cases, we need PCI bus reset hold and settlement delay as specified by PCI spec. PowerNV and pSeries platforms are running on top of different firmware and some of the delays have been covered by underly firmware (PowerNV). The patch makes the delays unified to be done in backend, instead of EEH core. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc/powernv: Reset root port in firmwareGavin Shan2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Resetting root port has more stuff to do than that for PCIe switch ports and we should have resetting root port done in firmware instead of the kernel itself. The problem was introduced by commit 5b2e198e ("powerpc/powernv: Rework EEH reset"). Cc: linux-stable <stable@vger.kernel.org> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc/pseries: Fix overwritten PE stateGavin Shan2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In pseries_eeh_get_state(), EEH_STATE_UNAVAILABLE is always overwritten by EEH_STATE_NOT_SUPPORT because of the missed "break" there. The patch fixes the issue. Reported-by: Joe Perches <joe@perches.com> Cc: linux-stable <stable@vger.kernel.org> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc/powernv: Fix endless reporting frozen PEGavin Shan2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Once one specific PE has been marked as EEH_PE_ISOLATED, it's in the middile of recovery or removed permenently. We needn't report the frozen PE again. Otherwise, we will have endless reporting same frozen PE. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc/eeh: No hotplug on permanently removed devGavin Shan2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The issue was detected in a bit complicated test case where we have multiple hierarchical PEs shown as following figure: +-----------------+ | PE#3 p2p#0 | | p2p#1 | +-----------------+ | +-----------------+ | PE#4 pdev#0 | | pdev#1 | +-----------------+ PE#4 (have 2 PCI devices) is the child of PE#3, which has 2 p2p bridges. We accidentally had less-known scenario: PE#4 was removed permanently from the system because of permanent failure (e.g. exceeding the max allowd failure times in last hour), then we detects EEH errors on PE#3 and tried to recover it. However, eeh_dev instances for pdev#0/1 were not detached from PE#4, which was still connected to PE#3. All of that was because of the fact that we rely on count-based pcibios_release_device(), which isn't reliable enough. When doing recovery for PE#3, we still apply hotplug on PE#4 and pdev#0/1, which are not valid any more. Eventually, we run into kernel crash. The patch fixes above issue from two aspects. For unplug, we simply skip those permanently removed PE, whose state is (EEH_PE_STATE_ISOLATED && !EEH_PE_STATE_RECOVERING) and its frozen count should be greater than EEH_MAX_ALLOWED_FREEZES. For plug, we marked all permanently removed EEH devices with EEH_DEV_REMOVED and return 0xFF's on read its PCI config so that PCI core will omit them. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc/eeh: Allow to disable EEHGavin Shan2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch introduces bootarg "eeh=off" to disable EEH functinality. Also, it creates /sys/kerenl/debug/powerpc/eeh_enable to disable or enable EEH functionality. By default, we have the functionality enabled. For PowerNV platform, we will restore to have the conventional mechanism of clearing frozen PE during PCI config access if we're going to disable EEH functionality. Conversely, we will rely on EEH for error recovery. The patch also fixes the issue that we missed to cover the case of disabled EEH functionality in function ioda_eeh_event(). Those events driven by interrupt should be cleared to avoid endless reporting. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc/eeh: Use cached capability for log dumpGavin Shan2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When calling into eeh_gather_pci_data() on pSeries platform, we possiblly don't have pci_dev instance yet, but eeh_dev is always ready. So we use cached capability from eeh_dev instead of pci_dev for log dump there. In order to keep things unified, we also cache PCI capability positions to eeh_dev for PowerNV as well. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc/eeh: Avoid I/O access during PE resetGavin Shan2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have suffered recrusive frozen PE a lot, which was caused by IO accesses during the PE reset. Ben came up with the good idea to keep frozen PE until recovery (BAR restore) gets done. With that, IO accesses during PE reset are dropped by hardware and wouldn't incur the recrusive frozen PE any more. The patch implements the idea. We don't clear the frozen state until PE reset is done completely. During the period, the EEH core expects unfrozen state from backend to keep going. So we have to reuse EEH_PE_RESET flag, which has been set during PE reset, to return normal state from backend. The side effect is we have to clear frozen state for towice (PE reset and clear it explicitly), but that's harmless. We have some limitations on pHyp. pHyp doesn't allow to enable IO or DMA for unfrozen PE. So we don't enable them on unfrozen PE in eeh_pci_enable(). We have to enable IO before grabbing logs on pHyp. Otherwise, 0xFF's is always returned from PCI config space. Also, we had wrong return value from eeh_pci_enable() for EEH_OPT_THAW_DMA case. The patch fixes it too. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc/powernv: Use EEH PCI config accessorsGavin Shan2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For EEH PowerNV backends, they need use their own PCI config accesors as the normal one could be blocked during PE reset. The patch also removes necessary parameter "hose" for the function ioda_eeh_bridge_reset(). Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc/eeh: Block PCI-CFG access during PE resetGavin Shan2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We've observed multiple PE reset failures because of PCI-CFG access during that period. Potentially, some device drivers can't support EEH very well and they can't put the device to motionless state before PE reset. So those device drivers might produce PCI-CFG accesses during PE reset. Also, we could have PCI-CFG access from user space (e.g. "lspci"). Since access to frozen PE should return 0xFF's, we can block PCI-CFG access during the period of PE reset so that we won't get recrusive EEH errors. The patch adds flag EEH_PE_RESET, which is kept during PE reset. The PowerNV/pSeries PCI-CFG accessors reuse the flag to block PCI-CFG accordingly. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc/powernv: Remove fields in PHB diag-data dumpGavin Shan2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some fields (e.g. LEM, MMIO, DMA) in PHB diag-data dump, it's meaningless to print them if they have non-zero value in the corresponding mask registers because we always have non-zero values in the mask registers. The patch only prints those fieds if we have non-zero values in the primary registers (e.g. LEM, MMIO, DMA status) so that we can save couple of lines. The patch also removes unnecessary spare line before "brdgCtl:" and two leading spaces as prefix in each line as Ben suggested. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc/powernv: Move PNV_EEH_STATE_ENABLED aroundGavin Shan2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The flag PNV_EEH_STATE_ENABLED is put into pnv_phb::eeh_state, which is protected by CONFIG_EEH. We needn't that. Instead, we can have pnv_phb::flags and maintain all flags there, which is the purpose of the patch. The patch also renames PNV_EEH_STATE_ENABLED to PNV_PHB_FLAG_EEH. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * | powerpc/powernv: Remove PNV_EEH_STATE_REMOVEDGavin Shan2014-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | The PHB state PNV_EEH_STATE_REMOVED maintained in pnv_phb isn't so useful any more and it's duplicated to EEH_PE_ISOLATED. The patch replaces PNV_EEH_STATE_REMOVED with EEH_PE_ISOLATED. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | | Merge tag 'devicetree-for-3.16' of ↵Linus Torvalds2014-06-04
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux into next Pull DeviceTree updates from Rob Herring: - Another round of clean-up of FDT related code in architecture code. This removes knowledge of internal FDT details from most architectures except powerpc. - Conversion of kernel's custom FDT parsing code to use libfdt. - DT based initialization for generic serial earlycon. The introduction of generic serial earlycon support went in through the tty tree. - Improve the platform device naming for DT probed devices to ensure unique naming and use parent names instead of a global index. - Fix a race condition in of_update_property. - Unify the various linker section OF match tables and fix several function prototype errors. - Update platform_get_irq_byname to work in deferred probe cases. - 2 binding doc updates * tag 'devicetree-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (58 commits) of: handle NULL node in next_child iterators of/irq: provide more wrappers for !CONFIG_OF devicetree: bindings: Document micrel vendor prefix dt: bindings: dwc2: fix required value for the phy-names property of_pci_irq: kill useless variable in of_irq_parse_pci() of/irq: do irq resolution in platform_get_irq_byname() of: Add a testcase for of_find_node_by_path() of: Make of_find_node_by_path() handle /aliases of: Create unlocked version of for_each_child_of_node() lib: add glibc style strchrnul() variant of: Handle memory@0 node on PPC32 only pci/of: Remove dead code of: fix race between search and remove in of_update_property() of: Use NULL for pointers of: Stop naming platform_device using dcr address of: Ensure unique names without sacrificing determinism tty/serial: pl011: add DT based earlycon support of/fdt: add FDT serial scanning for earlycon of/fdt: add FDT address translation support serial: earlycon: add DT support ...
| * | | Merge branch 'dt-bus-name' into for-nextRob Herring2014-05-13
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| * | | of/fdt: update of_get_flat_dt_prop in prep for libfdtRob Herring2014-04-30
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make of_get_flat_dt_prop arguments compatible with libfdt fdt_getprop call in preparation to convert FDT code to use libfdt. Make the return value const and the property length ptr type an int. Signed-off-by: Rob Herring <robh@kernel.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Grant Likely <grant.likely@linaro.org> Tested-by: Stephen Chivers <schivers@csc.com>
* | | powerpc/powernv: Reset root port in firmwareGavin Shan2014-05-11
| |/ |/| | | | | | | | | | | | | | | | | | | Resetting root port has more stuff to do than that for PCIe switch ports and we should have resetting root port done in firmware instead of the kernel itself. The problem was introduced by commit 5b2e198e ("powerpc/powernv: Rework EEH reset"). Cc: linux-stable <stable@vger.kernel.org> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-08 21:30:00 -0400