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* powerpc/book3e-64: Move the default cpu table entryKumar Gala2009-08-28
| | | | | | | | | Move the default cpu entry table for CONFIG_PPC_BOOK3E_64 to the very end since we will probably want to support both 32-bit and 64-bit kernels for some processors that are higher up in the list. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Add AMCC 460EX/460GT Rev. B support to cputable.cStefan Roese2009-08-19
| | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Remaining 64-bit Book3E supportBenjamin Herrenschmidt2009-08-19
| | | | | | | | This contains all the bits that didn't fit in previous patches :-) This includes the actual exception handlers assembly, the changes to the kernel entry, other misc bits and wiring it all up in Kconfig. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Add 2.06 tlbie mnemonicsMilton Miller2009-05-21
| | | | | | | | | | | This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards compatibilty for CPUs before 2.06. Only useful for bare metal systems. Signed-off-by: Milton Miller <miltonm@bga.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/pseries: Really fix the oprofile CPU type on pseriesBenjamin Herrenschmidt2009-05-15
| | | | | | | | | | | My previous pach for fixing the oprofile CPU type got somewhat mismerged (by my fault) when it collided with another related patch. This should finally (fingers crossed) fix the whole thing. We make sure we keep the -old- oprofile type and CPU type whenever one of them was specified in the first pass through the function. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Fix setting of oprofile cpu typeBenjamin Herrenschmidt2009-05-01
| | | | | | | | | | | | commit 2657dd4e301d4841ed67a4fac7d145ad8f3e1b28 introduced a bug where we would now always override the "real" oprofile CPU type with the "compatible" one provided by a pseudo-PVR in the device-tree which is incorrect and breaks oprofile on all current configs since the "compatible" ones aren't yet recognized. This fixes it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc adjust oprofile_cpu_type version 3Michael Wolf2009-05-01
| | | | | | | | | | | | | Oprofile is changing the naming it is using for the compatibility modes. Instead of having compat-power<x>, oprofile will go to family naming convention and use ibm-compat-v<x>. Currently only ibm-compat-v1 will be defined. The notion of compatibility events just started with POWER6. So there is no way that any other tool could exist that is using these oprofile_cpu_type strings we want to change. Signed-off-by: Mike Wolf <mjw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* Revert "powerpc: Add support for early tlbilx opcode"Kumar Gala2009-04-23
| | | | | | | This reverts commit e9965577406a2148ade97b5e0ce7c448b4ba4ef6. Our HW guys were able to fix this so it never sees the light of day. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc: Add support for early tlbilx opcodeKumar Gala2009-04-07
| | | | | | | | During the ISA 2.06 development the opcode for tlbilx changed and some early implementations used to old opcode. Add support for a MMU_FTR fixup to deal with this. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mm: e300c2/c3/c4 TLB errata workaroundKumar Gala2009-03-23
| | | | | | | | | | | | | Complete workaround for DTLB errata in e300c2/c3/c4 processors. Due to the bug, the hardware-implemented LRU algorythm always goes to way 1 of the TLB. This fix implements the proposed software workaround in form of a LRW table for chosing the TLB-way. Based on patch from David Jander <david@protonic.nl> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/oprofile: Enable support for ppc750 processorsOctavian Purdila2009-03-11
| | | | | | | | This patch enables oprofile for all 3 FX variants and GX variant of the 750 processor. Signed-off-by: Octavian Purdila <opurdila@ixiacom.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Make sure we copy all cpu_spec features except PMC related onesMichael Ellerman2009-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | When identify_cpu() is called a second time with a logical PVR, it only copies a subset of the cpu_spec fields so as to avoid overwriting the performance monitor fields that were initialized based on the real PVR. However some of the other, non performance monitor related fields are also not copied: * pvr_mask * pvr_value * mmu_features * machine_check The fact that pvr_mask is not copied can result in show_cpuinfo() showing the cpu as "unknown", if we override an unknown PVR with a logical one - as reported by Shaggy. So change the logic to copy all fields, and then put back the PMC related ones in the case that we're overwriting a real PVR with a logical one. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Deindentify identify_cpu()Michael Ellerman2009-03-11
| | | | | | | | | The for-loop body of identify_cpu() has gotten a little big, so move the loop body logic into a separate function. No other changes. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/fsl-booke: Add support for tlbilx instructionsKumar Gala2009-03-09
| | | | | | | | The e500mc core supports the new tlbilx instructions that do core local invalidates and also provide us the ability to take down all TLB entries matching a given PID. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* AMCC PPC 460SX redwood SoC platform initial frameworkMadhulika Madishetty2009-02-14
| | | | | | | | | | | | | This patch contains initial framework for the AMCC Redwood board. Signed-off-by: Madhulika Madishetty <mmadishetty@amcc.com> Signed-off-by: Tirumala Marri <tmarri@amcc.com> Signed-off-by: Feng Kan <fkan@amcc.com> Signed-off-by: Vidhyananth Venkatasamy <vvenkatasamy@amcc.com> Signed-off-by: Preetesh Parekh <pparekh@amcc.com> Acked-by: Loc Ho <lho@amcc.com> Acked-by: Feng Kan <fkan@amcc.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* powerpc/fsl-booke: Cleanup init/exception setup to be runtimeKumar Gala2009-01-28
| | | | | | | | | | | | | | | | | | We currently have a few variants of fsl-booke processors (e500v1, e500v2, e500mc, and e200). They all have minor differences that we had previously been handling via ifdefs. To move towards having this support the following changes have been made: * PID1, PID2 only exist on e500v1 & e500v2 and should not be accessed on e500mc or e200. We use MMUCFG[NPIDS] to determine which case we are since we only touch PID1/2 in extremely early init code. * Not all IVORs exist on all the processors so introduce cpu_setup functions for each variant to setup the proper IVORs that are either unique or exist but have some variations between the processors Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mm: Introduce MMU featuresBenjamin Herrenschmidt2008-12-20
| | | | | | | | | | | | We're soon running out of CPU features and I need to add some new ones for various MMU related bits, so this patch separates the MMU features from the CPU features. I moved over the 32-bit MMU related ones, added base features for MMU type families, but didn't move over any 64-bit only feature yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* powerpc/4xx: Extended DCR support v2Benjamin Herrenschmidt2008-12-20
| | | | | | | | | | | | | This adds supports to the "extended" DCR addressing via the indirect mfdcrx/mtdcrx instructions supported by some 4xx cores (440H6 and later). I enabled the feature for now only on AMCC 460 chips. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* powerpc/virtex5: Fix Virtex5 machine check handlingGrant Likely2008-12-05
| | | | | | | | | | | | | The 440x5 core in the Virtex5 uses the 440A type machine check (ie, they have MCSRR0/MCSRR1). They thus need to call the appropriate fixup function to hook the right variant of the exception. Without this, all machine checks become fatal due to loss of context when entering the exception handler. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* powerpc/40x: Add AMCC PowerPC 405EZ to cputableJosh Boyer2008-10-17
| | | | | | This adds the AMCC PowerPC 405EZ chip to the cputable Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* powerpc: Expose PMCs & cache topology in sysfs on 32-bitBenjamin Herrenschmidt2008-08-20
| | | | | | | | | | | | | | | The file arch/powerpc/kernel/sysfs.c is currently only compiled for 64-bit kernels. It contain code to register CPU sysdevs in sysfs and add various properties such as cache topology and raw access by root to performance monitor counters (PMCs). A lot of that can be re-used as is on 32-bits. This makes the file be built for both, with appropriate ifdef'ing for the few bits that are really 64-bit specific, and adds some support for the raw PMCs for 75x and 74xx processors. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* powerpc: Fix boot problem due to AT_BASE_PLATFORM changeNathan Lynch2008-07-25
| | | | | | | | | | | | Commit 9115d13453dee22473a1e8cacc90a8d64a9c4bc9 ("powerpc: Enable AT_BASE_PLATFORM aux vector") broke boot on 32-bit powerpc systems; we have to use PTRRELOC to initialize powerpc_base_platform this early in boot. Bug reported by Jon Smirl. Signed-off-by: Nathan Lynch <ntl@pobox.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Enable AT_BASE_PLATFORM aux vectorNathan Lynch2008-07-25
| | | | | | | | | Stash the first platform string matched by identify_cpu() in powerpc_base_platform, and supply that to the ELF loader for the value of AT_BASE_PLATFORM. Signed-off-by: Nathan Lynch <ntl@pobox.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Indicate which oprofile counters to use while in compat modeTorez Smith2008-07-21
| | | | | | | | | | | | | | | | | | | | | | While running on a system with new hardware and a kernel where the cpu_specs[] table does not recognize the new hardware, the identify_cpu() routine will select the default case as it searches through cpu_specs[] in an attempt to match the real PVR. Once the default case is selected, non of the oprofile counters and/or fields have been set up or defined. When identify_cpu() is called once more with the logical PVR, some of the cpu specific fields are replaced with the exception of the oprofile related ones. However, in the case where we have actually taken the default case while searching for the real PVR, we need to tell oprofile that we are now running in compatibility mode so it can pick up the correct counters. We do this by setting the oprofile_cpu_type field to be that taken from the cpu_specs[] for the cpu we are now emulating. This change will detect that we are now altering the real PVR and determine if we also need to update the oprofile_cpu_type field. Signed-off-by: Torez Smith <lnxtorez@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Add PPC_FEATURE_PSERIES_PERFMON_COMPATNathan Lynch2008-07-14
| | | | | | | | | | | | | | | | | | | | | Background from Maynard Johnson: As of POWER6, a set of 32 common events is defined that must be supported on all future POWER processors. The main impetus for this compat set is the need to support partition migration, especially from processor P(n) to processor P(n+1), where performance software that's running in the new partition may not be knowledgeable about processor P(n+1). If a performance tool determines it does not support the physical processor, but is told (via the PPC_FEATURE_PSERIES_PERFMON_COMPAT bit) that the processor supports the notion of the PMU compat set, then the performance tool can surface just those events to the user of the tool. PPC_FEATURE_PSERIES_PERFMON_COMPAT indicates that the PMU supports at least this basic subset of events which is compatible across POWER processor lines. Signed-off-by: Nathan Lynch <ntl@pobox.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/virtex: add Xilinx 440 cpu to the cputableJohn Linn2008-07-04
| | | | | | | | Updates the cputable to include the 440 processor found in the Xilinx Virtex5 FXT FPGA. Signed-off-by: John Linn <john.linn@xilinx.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
* powerpc: Split out do_feature_fixups() from cputable.cMichael Ellerman2008-06-30
| | | | | | | | | | | | | The logic to patch CPU feature sections lives in cputable.c, but these days it's used for CPU features as well as firmware features. Move it into it's own file for neatness and as preparation for some additions. While we're moving the code, we pull the loop body logic into a separate routine, and remove a comment which doesn't apply anymore. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* powerpc: Add PPC_NOP_INSTR, a hash define for the preferred nop instructionMichael Ellerman2008-06-30
| | | | | | | | | A bunch of code has hard-coded the value for a "nop" instruction, it would be nice to have a #define for it. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* powerpc: Add cputable entry for Power7 architected modeJoel Schopp2008-06-30
| | | | | | | | Add an entry for Power7 architected mode and add "(raw)" to Power7 raw mode to distinguish it more clearly. Signed-off-by: Joel Schopp <jschopp@austin.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* powerpc: Add cputable entry for POWER7Michael Neuling2008-06-30
| | | | | | | | | | Add a cputable entry for the POWER7 processor. Also tell firmware that we know about POWER7. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Joel Schopp <jschopp@austin.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* Merge branch 'next' of ↵Paul Mackerras2008-06-29
|\ | | | | | | master.kernel.org:/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx
| * Revert "[POWERPC] 4xx: Fix 460GT support to not enable FPU"Josh Boyer2008-06-11
| | | | | | | | | | | | | | | | | | This reverts commit acb0142bf01c0ebe18f09e37814451ee6a873e27. AMCC has indicated that the PPC 460GT does have FPU support. This revert enables the FPU for those chips again. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* | powerpc/85xx: add DOZE/NAP support for e500 coreKumar Gala2008-06-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The e500 core enter DOZE/NAP power-saving modes when the core go to cpu_idle routine. The power management default running mode is DOZE, If the user echo 1 > /proc/sys/kernel/powersave-nap the system will change to NAP running mode. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/booke: Add support for new e500mc coreKumar Gala2008-06-18
|/ | | | | | | | | | | | | | | The new e500mc core from Freescale is based on the e500v2 but with the following changes: * Supports only the Enhanced Debug Architecture (DSRR0/1, etc) * Floating Point * No SPE * Supports lwsync * Doorbell Exceptions * Hypervisor * Cache line size is now 64-bytes (e500v1/v2 have a 32-byte cache line) Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Fix default cputable entries for e200 and e500 familiesPaul Mackerras2008-05-12
| | | | | | | | Commit 76bc080ef5a34aedb63e1691f28c6b42f3468e4e ("POWERPC] Make default cputable entries reflect selected CPU family") added default entries for the e200 and e500 families, but missed a closing brace on those entries, as pointed out by David Gibson. This adds the closing braces. Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] Make default cputable entries reflect selected CPU familyBenjamin Herrenschmidt2008-05-09
| | | | | | | | | | | | Changes the cputable so that various CPU families that have an exclusive CONFIG_ option have a more sensible default entry to use if the specific processor hasn't been identified. This makes the kernel more generally useful when booted on an unknown PVR for things like new 4xx variants. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] 4xx: Fix 460GT support to not enable FPUStefan Roese2008-04-24
| | | | | | | The AMCC 460GT doesn't have an FPU so let's not enable support for it. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: Add AMCC 460EX/460GT support to cputable.c & cpu_setup_44x.SStefan Roese2008-03-26
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic support for the AMCC 460EX/460GT PPC's to arch/powerpc. Currently those PPC's are still based on a 440 core and *not* a 460 core. Here some basic features of those SoC's: 460EX: - Up to 1.2GHz, 32kB L1 I-cache and D-cache, 256kB L2-cache, FPU - 1 * PCI (max 66MHz), 2 * PCIe (one 4-lane, one 1-lane) - 2 * GBit Ethernet with TCP/IP acceleration - USB 2.0 Host/Device OTG and Host interface - SATA controller - Optional security feature 460GT (only changes to 460EX): - 4 * GBit Ethernet with TCP/IP acceleration - RapidIO - No SATA - No USB Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC} Add oprofile support for e300Andy Fleming2008-02-06
| | | | | | | | The e300 c3 and c4 variants support hardware performance monitor counters which are identical to those found in the e500. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Made FSL Book-E PMC support more genericAndy Fleming2008-02-06
| | | | | | | | | | Some of the more recent e300 cores have the same performance monitor implementation as the e500. e300 isn't book-e, so the name isn't really appropriate. In preparation for e300 support, rename a bunch of fsl_booke things to say fsl_emb (Freescale Embedded Performance Monitors). Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 4xx: Add PowerPC 440EP Rev CSean MacLennan2008-01-25
| | | | | | | | This adds the 440EP revision C PVR to the CPU table. The chip has an FPU on it, so we also match the logical PVR Signed-off-by: Sean MacLennan <smaclennan@pikatech.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: Add 405EXr to cputableStefan Roese2008-01-25
| | | | | | | | This patch adds the 405EXr to the powerpc cuptable. Basically the 405EXr is a 405EX with only one EMAC and only one PCIe interface. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] Conditionally compile e200 and e500 platforms in cputableJosh Boyer2007-12-24
| | | | | | | | The e200 and e500 platforms are separated in various parts of the kernel with ifdefs, most notably reg_booke.h and traps.c. The new machine_check rework requires them to be similarly separated in cputable.c to avoid compile errors. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: Correct 440GRx machine_check callbackValentine Barshak2007-12-23
| | | | | | | Correct the PowerPC 440GRx machine check callback. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] Reworking machine check handling and Fix 440/440ABenjamin Herrenschmidt2007-12-23
| | | | | | | | | | | | | | | This adds a cputable function pointer for the CPU-side machine check handling. The semantic is still the same as the old one, the one in ppc_md. overrides the one in cputable, though ultimately we'll want to change that so the CPU gets first. This removes CONFIG_440A which was a problem for multiplatform kernels and instead fixes up the IVOR at runtime from a setup_cpu function. The "A" version of the machine check also tweaks the regs->trap value to differenciate the 2 versions at the C level. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] add e300c4 entry to cputableLi Yang2007-12-11
| | | | | Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 4xx: Workaround for the 440EP(x)/GR(x) processors identical PVR issue.Valentine Barshak2007-11-01
| | | | | | | | | | | | | | | | | PowerPC 440EP(x) 440GR(x) processors have the same PVR values, since they have identical cores. However, FPU is not supported on GR(x) and enabling APU instruction broadcast in the CCR0 register (to enable FPU) may cause unpredictable results. There's no safe way to detect FPU support at runtime. This patch provides a workarund for the issue. We use a POWER6 "logical PVR approach". First, we identify all EP(x) and GR(x) processors as GR(x) ones (which is safe). Then we check the device tree cpu path. If we have a EP(x) processor entry, we call identify_cpu again with PVR | 0x8. This bit is always 0 in the real PVR. This way we enable FPU only for 440EP(x). Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: Add AMCC 405EX support to cputable.cStefan Roese2007-10-11
| | | | | Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] Fix performance monitor on machines with logical PVRPaul Mackerras2007-10-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some IBM machines supply a "logical" PVR (processor version register) value in the device tree in the cpu nodes rather than the real PVR. This is used for instance to indicate that the processors in a POWER6 partition have been configured by the hypervisor to run in POWER5+ mode rather than POWER6 mode. To cope with this, we call identify_cpu a second time with the logical PVR value (the first call is with the real PVR value in the very early setup code). However, POWER5+ machines can also supply a logical PVR value, and use the same value (the value that indicates a v2.04 architecture compliant processor). This causes problems for code that uses the performance monitor (such as oprofile), because the PMU registers are different in POWER6 (even in POWER5+ mode) from the real POWER5+. This change works around this problem by taking out the PMU information from the cputable entries for the logical PVR values, and changing identify_cpu so that the second call to it won't overwrite the PMU information that was established by the first call (the one with the real PVR), but does update the other fields. Specifically, if the cputable entry for the logical PVR value has num_pmcs == 0, none of the PMU-related fields get used. So that we can create a mixed cputable entry, we now make cur_cpu_spec point to a single static struct cpu_spec, and copy stuff from cpu_specs[i] into it. This has the side-effect that we can now make cpu_specs[] be initdata. Ultimately it would be good to move the PMU-related fields out to a separate structure, pointed to by the cputable entries, and change identify_cpu so that it saves the PMU info pointer, copies the whole structure, and restores the PMU info pointer, rather than identify_cpu having to list all the fields that are *not* PMU-related. Signed-off-by: Paul Mackerras <paulus@samba.org> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* [POWERPC] 4xx: 440EPx/GRx incorrect write to DDR SDRAM errata workaroundValentine Barshak2007-10-03
| | | | | | | | | | Add a workaround for PowerPC 440EPx/GRx incorrect write to DDR SDRAM errata. Data can be written to wrong address in SDRAM when write pipelining enabled on plb0. We disable it in the cpu_setup for these processors at early init. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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