| Commit message (Collapse) | Author | Age |
|---|
| |
|
|
|
|
|
|
|
|
| |
For cuImage format it's necessary to provide clock fixups since u-boot will
not pass necessary clock frequency into the dtb included into cuImage so we
implement the clock fixups as defined in the technical documentation for the
board and update header file with the basic register definitions.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This patch adds support for 405GPr processors with optional
new mode strapping. ibm405gp_fixup_clocks() can now be used
for 405GP and 405GPr CPUs.
This is in preparation of porting the cpci405 platform support
from arch/ppc to arch/powerpc.
This patch also adds ibm405ep_fixup_clocks() to support
405EP CPUs from the boot wrapper.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This reworks the boot wrapper library function that probes
the chip clocks. Better separate the base function that is
used on 440GX,SPe,EP,... from the uart fixups as those need
different device-tree path on different processors.
Also, rework the function itself based on the arch/ppc code
from Eugene Surovegin which I find more readable, and which
handles one more bypass case. Also handle the subtle difference
between 440EP/EPx and 440SPe/GX, on the former, PerClk is derived
from the PLB clock while on the later, it's derived from the OPB.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
| |
|
|
|
|
|
|
| |
This adds a function to the bootwrapper 4xx library to decode memory
size on 440SPE processors.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Brings EP405 support to arch/powerpc. The IRQ routing for the CPLD
comes from a device-tree property, PCI is working to the point where
I can see the video card, USB device, and south bridge.
This should work with both EP405 and EP405PC.
I've not totally figured out how IRQs are wired on this hardware
though, thus at this stage, expect only USB interrupts working,
pretty much the same as what arch/ppc did.
Also, the flash, nvram, rtc and temp control still have to be wired.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
| |
|
|
|
|
|
|
| |
Bootwrapper code for AMCC PPC440EPx Sequoia.
Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
| |
|
|
|
|
|
|
| |
Add a bootwrapper for the AMCC 440EP Bamboo Eval board. This also adds a
common fixup_clock function for all 440EP(x) chips.
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
|
|
|
Make the fixup_memsize function common for all of 4xx as several chips share
the same SDRAM controller. Also add functions to reset 40x chips and quiesce
the ethernet.
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
