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| | * | | | MIPS: inst.h: define MT yield opPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The opcode for the MT ASE yield instruction within the spec3 group was missing. This patch adds it for use by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: inst.h: define COP0 wait opPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The func field for the wait instruction was missing from inst.h - this patch adds it. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: MT: define write_c0_tchalt macroPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define a macro to write to the current TCs TCHalt register. This will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: add kmap_noncoherent to wire a cached non-coherent TLB entryPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is identical to kmap_coherent apart from the cache coherency attribute used for the TLB entry, so kmap_coherent is abstracted to kmap_prot which is then called for both kmap_coherent & kmap_noncoherent. This will be used by a subsequent patch. Suggested-by: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: CPC: provide locking functionsPaul Burton2014-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides functions to lock & unlock access to the "core-other" register region of the CPC. Without performing appropriate locking it is possible for code using this region to be preempted or to race with code on another VPE within the same core, with one changing the core which the "core-other" region is acting upon at an inopportune time for the other. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: CPC: provide functions to retrieve register addressesPaul Burton2014-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces addr_ functions in addition to the existing read_ & write_ functions. The new functions simply return the address of the appropriate CPC register rather than performing a memory access. This will be used in a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: introduce cpu_coherent_maskPaul Burton2014-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a mask of CPUs which are currently known to be operating coherently. This is setup initially to be all present CPUs, but in a subsequent patch CPUs in a MIPS Coherent Processing System will be cleared in this mask as they enter non-coherent idle states. This will be used in order to determine when a CPU within a CPS system may need to be powered back up, but may also be used in future to optimise away wakeups for cache operations or TLB invalidations. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: support for generic clockevents broadcastPaul Burton2014-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for generic clockevents broadcast using the a dummy clockevent device and the tick_broadcast function introduced by commit 12ad10004645 "clockevents: Add generic timer broadcast function". Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: allow R4K clockevent device to function regardless of GICPaul Burton2014-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having the GIC clockevent driver compiled should not prevent the R4K timer clockevent driver from functioning. One will be selected as the CPU local timer based upon their priorities and the other may simply be unused or in the case of the GIC timer may be used as the tick broadcast device. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: mark R4K clockevent device with CLOCK_EVT_FEAT_PERCPUPaul Burton2014-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CLOCK_EVT_FEAT_PERCPU flag indicates that a clockevent device is only configurable by the CPU for which it is registered, and thus cannot be used as the tick broadcast device. That property is true of the R4K timer, which is inaccessible from other cores. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: mark R4K clockevent device with CLOCK_EVT_FEAT_C3STOPPaul Burton2014-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a core enters a clock off or power down state its CP0 counter will be stopped along with it. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: allow GIC clockevent device config from other CPUsPaul Burton2014-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows the GIC clockevent device for a CPU to be configured by another CPU. This makes GIC clockevent devices suitable for use as the tick broadcast device, where formerly the GIC timer local to the configuring CPU would have been configured incorrectly. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: mark GIC clockevent device with CLOCK_EVT_FEAT_C3STOPPaul Burton2014-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although the GIC counter will continue when a core is in a low power state and it will still trigger interrupts, the core will be incapable of servicing those interrupts rendering them useless. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: PM: Implement PM helper macrosJames Hogan2014-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement assembler helper macros in asm/pm.h for platform code to use for saving context across low power states - for example suspend to RAM or powered down cpuidle states. Macros are provided for saving and restoring the main CPU context used by C code and doing important configuration which must be done very early during resume. Notably EVA needs segmentation control registers to be restored before the stack or dynamically allocated memory is accessed, so that state is saved in global data. Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: tlb-r4k: Add CPU PM callback to reconfigure TLBJames Hogan2014-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a CPU power management callback for the r4k TLB which reconfigures it after the CPU leaves a powered down state. Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: c-r4k: Add CPU PM callback for coherencyJames Hogan2014-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement a CPU power management callback for the r4k cache, to set up coherency again after leaving a powered down state. Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: traps: Add CPU PM callback for trap configurationJames Hogan2014-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement a CPU power management callback for restoring trap related CPU configuration after CPU power up from a low power state. The following state is restored: - Status register - HWREna register - Exception vector configuration registers - Context/XContext register Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | | | MIPS: PM: Add CPU PM callbacks for general CPU contextJames Hogan2014-04-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a CPU power management notifier callback for preserving general CPU context. The CPU PM callbacks will be triggered by the powering down of CPU cores, for example by cpuidle drivers & in the future by suspend to RAM implementations. The current state preserved is mostly related to the process context: - FPU - DSP - ASID - UserLocal - Watch registers Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | | | | MIPS: SNI: Remove USE_GENERIC_EARLY_PRINTK_8250Thomas Bogendoerfer2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SNI RM code has its own EARLY_PRINTK support no need for some generic 8250 stuff. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6715/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: Alchemy: Default to noncoherent IO on Au1200 ABManuel Lauss2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_DMA_COHERENT is no longer set; default to noncoherent io on Au1200 revision AB to make USB work. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/6745/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: Octeon: Add PCIe2 support in arch_setup_msi_irq()Eunbong Song2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In arch_setup_msi_irq(), there is no case for PCIe2. So board which have PCIe2 functionality fails to boot with "Kernel panic - not syncing: arch_setup_msi_irq: Invalid octeon_dma_bar_type" message. This patch solve this problem. Signed-off-by: Eunbong Song <eunb.song@samsung.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/6747/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: defconfigs: add MTD_SPI_NOR (new dependency for M25P80)Brian Norris2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These defconfigs contain the CONFIG_M25P80 symbol, which is now dependent on the MTD_SPI_NOR symbol. Add CONFIG_MTD_SPI_NOR to satisfy the new dependency. At the same time, drop the now-nonexistent CONFIG_MTD_CHAR symbol. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Huang Shijie <b32955@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: linux-mtd@lists.infradead.org Patchwork: https://patchwork.linux-mips.org/patch/6878/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: Add __SANE_USERSPACE_TYPES__ to asm/types.h for LL64Aaro Koskinen2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow 64-bit userspace programs to use ll64 types. The define name comes from commit 2c9c6ce0199a4d252e20c531cfdc9d24e39235c0 (powerpc: Add __SANE_USERSPACE_TYPES__ to asm/types.h for LL64). The patch allows to compile perf on MIPS64 and eliminates the following warnings: tests/attr.c:74:4: error: format '%llu' expects argument of type 'long long unsigned int', but argument 6 has type '__u64' [-Werror=format=] Signed-off-by: Aaro Koskinen <aaro.koskinen@nsn.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/6890/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: Lemote 2F: cs5536: mfgpt: depend on !highresSebastian Andrzej Siewior2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This timer does not support oneshot mode and as such the system remains in periodic mode and won't support high res timers. This patch adds a note about this in Kconfig and lets it depend on !highres so users which want to use high timers don' stuck with this timer. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Cc: linux-mips@linux-mips.org Cc: Hua Yan <yanh@lemote.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Alex Smith <alex.smith@imgtec.com> Cc: Hongliang Tao <taohl@lemote.com> Cc: Wu Zhangjin <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6935/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: SMP: Remove plat_smp_ops cpus_done method.Ralf Baechle2014-05-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nothing was using the method and there isn't any need for this hook. This leaves smp_cpus_done() empty for the moment. As suggested by Paul Bolle <pebolle@tiscali.nl>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: DTS: Fix missing device_type="memory" property in memory nodesLeif Lindholm2014-05-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few platforms lack a 'device_type = "memory"' for their memory nodes, relying on an old ppc quirk in order to discover its memory. Add the missing data so that all parsing code can find memory nodes correctly. Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: John Crispin <blogic@openwrt.org> Signed-off-by: Grant Likely <grant.likely@linaro.org> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: Mark Rutland <mark.rutland@arm.com> Cc: <stable@vger.kernel.org> Cc: gaurav.minocha@alumni.ubc.ca Patchwork: https://patchwork.linux-mips.org/patch/6989/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: SEAD3: Introduce the use of the managed version of kzallocHimangi Saraogi2014-05-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves data allocated using kzalloc to managed data allocated using devm_kzalloc and cleans now unnecessary kfrees in probe and remove functions. Also, the now unnecessary labels out_mem and out are done away with. The error handling code is moved under if and return 0 is now at the end of the function. The following Coccinelle semantic patch was used for making the change: @platform@ identifier p, probefn, removefn; @@ struct platform_driver p = { .probe = probefn, .remove = removefn, }; @prb@ identifier platform.probefn, pdev; expression e, e1, e2; @@ probefn(struct platform_device *pdev, ...) { <+... - e = kzalloc(e1, e2) + e = devm_kzalloc(&pdev->dev, e1, e2) ... ?-kfree(e); ...+> } @rem depends on prb@ identifier platform.removefn; expression e; @@ removefn(...) { <... - kfree(e); ...> } Signed-off-by: Himangi Saraogi <himangi774@gmail.com> Acked-by: Julia Lawall <julia.lawall@lip6.fr> Tested-by: Markos Chandras <markos.chandras@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/6977/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: malta: Remove 'maybe_unused' attribute from ememsize{, _str}Markos Chandras2014-05-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First introduced in e6ca4e5bf11466b5e9423a1e4ea51a8216c4b9b6 "MIPS: malta: malta-memory: Add support for the 'ememsize' variable" but it is not needed since both variables are visible to the compiler. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: <stable@vger.kernel.org> # v3.15+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6985/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: Kconfig: Make MIPS_MT_SMP a regular Kconfig symbolMarkos Chandras2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Following the removal of SMTC, MIPS_MT_SMP is the only available MT/SMP option so make it a regular Kconfig symbol. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6720/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: MT: Remove SMTC supportRalf Baechle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nobody is maintaining SMTC anymore and there also seems to be no userbase. Which is a pity - the SMTC technology primarily developed by Kevin D. Kissell <kevink@paralogos.com> is an ingenious demonstration for the MT ASE's power and elegance. Based on Markos Chandras <Markos.Chandras@imgtec.com> patch https://patchwork.linux-mips.org/patch/6719/ which while very similar did no longer apply cleanly when I tried to merge it plus some additional post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to merge once upon a time. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: RM9000: Remove the now unused CPU_RM9000 definition.Ralf Baechle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: RM9000: Remove support for probing the CPU core.Ralf Baechle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: RM9000: Remove support for idle loop.Ralf Baechle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: Ralink: Remove surviving RM9000 bits.Ralf Baechle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: Remove code protected by CONFIG_SYS_HAS_CPU_RM9000.Ralf Baechle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RM9000 support was removed a while ago but this bit crept back in through commit 69f24d17 [MIPS: Optimize current_cpu_type() for better code.] which had been developed before but merged after RM9000 support was removed. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Reported-by: Paul Bolle <pebolle@tiscali.nl>
| * | | | | MIPS: BCM1480: Remove checks for CONFIG_SIBYTE_BCM1480_PROFPaul Bolle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two checks for CONFIG_SIBYTE_BCM1480_PROF in the tree since v2.6.15. The related Kconfig symbol has never been added to the tree. So these checks have always evaluated to false. Besides, one of these checks guards a call of sbprof_cpu_intr(). But that function is not defined. Remove all this. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/6981/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: MSP71xx: Remove checks for two macrosPaul Bolle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since v2.6.39 there are checks for CONFIG_MSP_HAS_DUAL_USB and checks for CONFIG_MSP_HAS_TSMAC in the code. The related Kconfig symbols have never been added. These checks have evaluated to false for three years now. Remove them and the code they have been hiding. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Cc: Alan Stern <stern@rowland.harvard.edu> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: linux-mips@linux-mips.org Cc: linux-usb@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/6982/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: Octeon: Remove checks for CONFIG_CAVIUM_GDBPaul Bolle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Three checks for CONFIG_CAVIUM_GDB were added in v2.6.29. But the Kconfig symbol CAVIUM_GDB was never added to the tree. Remove these checks. Also remove the last reference to octeon_get_boot_debug_flag(). There is no definition of that function anyway. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Tested-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>) Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/6976/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: PNX833x: Remove checks for CONFIG_I2C_PNX0105Paul Bolle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Checks for CONFIG_I2C_PNX0105 were added in v2.6.28. But the related Kconfig symbol has not been added to the tree. Remove these checks. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/6958/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: Remove CONFIG_PMCTWILED completelyPaul Bolle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 8b284dbc2200 ("MIPS: PNX Removing dead CONFIG_PMCTWILED") missed one reference to CONFIG_PMCTWILED in the code. It also missed one related reference to pmctwiled_setup(). Remove these references now. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/6957/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: Remove check for CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECCPaul Bolle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A check for CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC was added in v2.6.29, but without the related Kconfig symbol. Remove this check. Also remove the test for an "ecc_verbose" kernel parameter. It is undocumented and has no effect anyway. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/6955/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: c-r4k: Call R4600_HIT_CACHEOP_WAR_IMPL only for 32 byte cache lines.Ralf Baechle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R4600_HIT_CACHEOP_WAR_IMPL is only needed on R4600 v1.6 and the R4600 has data cache lines that are always 32 bytes so the call is pointless in r4k_blast_dcache_page_dc64. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: math-emu: Reduce microMIPS bloat.Ralf Baechle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move microMIPS32_to_MIPS32() to a separate file which only gets built for mipsMIPS configurations; for other configurations the optimizer eleminates calls to microMIPS32_to_MIPS32(). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: math-emu: Switch to using the MIPS rounding modes.Ralf Baechle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously math-emu was using the IEEE-754 constants internally. These were differing by having the constants for rounding to +/- infinity switched, so a conversion was necessary. This would be entirely avoidable if the MIPS constants were used throughout, so get rid of the bloat. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: math-emu: Nuke alternative names for IEEE-754 rounding modes.Ralf Baechle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: Sort out mm_isBranchInstr.Ralf Baechle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mm_isBranchInstr() did reside in the math emu code even though it logically is separate and also is used outside the math emu code. In addition GCC 4.9.0 leaves the following unnnecessarily bloated function body for a non-microMIPS configuration: <mm_isBranchInstr>: 105c: afa50004 sw a1,4(sp) 1060: afa60008 sw a2,8(sp) 1064: afa7000c sw a3,12(sp) 1068: 03e00008 jr ra 106c: 00001021 move v0,zero which stores arguments that are never going to be used on the stack frame. Move mm_isBranchInstr() from cp1emu.c to branch.c, then split mm_isBranchInstr() into a __mm_isBranchInstr() core and a mm_isBranchInstr() wrapper inline function which only invokes __mm_isBranchInstr() on microMIPS configurations. This shaves off 112 bytes off the kernel and improves code flow a bit. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: Disable MIPS16/microMIPS crap for platforms not supporting these ASEs.Ralf Baechle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: math-emu: Inline fpu_emulator_init_fpu()Ralf Baechle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: math-emu: Cleanup coding style.Ralf Baechle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | o Only define variables in the outermost block o One empty line at most o Format comments as per CodingStyle o Update FSF address in licensing term comment o Spell FPU and MIPS in all capitals. o Remove ####-type of lines in comments. o Try to make things a bit most consistent between sp_*.c / dp_*.c files. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: math-emu: Cleanup definition of structs describe sp/dp floats.Ralf Baechle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-11 02:05:19 -0400