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* [MIPS] Sibyte: Fixes for oneshot timer mode.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Remove blank line.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Swarm: Fix build failureThiemo Seufer2007-11-02
| | | | | Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Code cleanupsAtsushi Nemoto2007-11-02
| | | | | | | | | | | | | * Do not include unnecessary headers. * Do not mention time.README. * Do not mention mips_timer_ack. * Make clocksource_mips static. It is now dedicated to c0_timer. * Initialize clocksource_mips.read statically. * Remove null_hpt_read. * Remove an argument of plat_timer_setup. It is just a placeholder. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Remove now unused local_timer_interrupt.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP32: Fix address of 2nd serial interface.Ralf Baechle2007-11-02
| | | | | | Found by Giuseppe Sacco <giuseppe@eppesuigoccas.homedns.org>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SB1250: Use the right irqaction for the timer interrupt.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SB1250: Remove stray assignment of cpumask.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Fix names of the clockevent devices.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Build fixes / dead code removal.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] tb0219: Update copyright message.Ralf Baechle2007-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] MT: Fix bug in multithreaded kernels.Ralf Baechle2007-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When GDB writes a breakpoint into address area of inferior process the kernel needs to invalidate the modified memory in the inferior which is done by calling flush_cache_page which in turns calls r4k_flush_cache_page and local_r4k_flush_cache_page for VSMP or SMTC kernel via r4k_on_each_cpu(). As the VSMP and SMTC SMP kernels for 34K are running on a single shared caches it is possible to get away without interprocessor function calls. This optimization is implemented in r4k_on_each_cpu, so local_r4k_flush_cache_page is only ever called on the local CPU. This is where the following code in local_r4k_flush_cache_page() strikes: /* * If ownes no valid ASID yet, cannot possibly have gotten * this page into the cache. */ if (cpu_context(smp_processor_id(), mm) == 0) return; On VSMP and SMTC had a function of cpu_context() for each CPU(TC). So in case another CPU than the CPU executing local_r4k_cache_flush_page has not accessed the mm but one of the other CPUs has there may be data to be flushed in the cache yet local_r4k_cache_flush_page will falsely return leaving the I-cache inconsistent for the breakpoint. While the issue was discovered with GDB it also exists in local_r4k_flush_cache_range() and local_r4k_flush_cache(). Fixed by introducing a new function has_valid_asid which on MT kernels returns true if a mm is active on any processor in the system. This is relativly expensive since for memory acccesses in that loop cache misses have to be assumed but it seems the most viable solution for 2.6.23 and older -stable kernels. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: Remove CONFIG_TS_AU1X00_ADS7846 from defconfigs.Ralf Baechle2007-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Author: Ralf Baechle <ralf@linux-mips.org>Ralf Baechle2007-10-29
| | | | | | [MIPS] MSP71xx: Fix bitrot. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] sb1250: Enable GenBus IDE in defconfig.Maciej W. Rozycki2007-10-29
| | | | | | | Enable the onboard GenBus IDE interface in the default configuration. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] vmlinux.ld.S: correctly indent .data sectionFranck Bui-Huu2007-10-29
| | | | | Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] c-r3k: Implement flush_cache_range()Maciej W. Rozycki2007-10-29
| | | | | | | | | | | | | | Contrary to the belief of some, the R3000 and related processors did have caches, both a data and an instruction cache. Here is an implementation of r3k_flush_cache_page(), which is the processor-specific back-end for flush_cache_range(), done according to the spec in Documentation/cachetlb.txt. While at it, remove an unused local function: get_phys_page(), do some trivial formatting fixes and modernise debugging facilities. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Store sign-extend register values for PTRACE_GETREGSAtsushi Nemoto2007-10-29
| | | | | | | | | A comment on ptrace_getregs() states "Registers are sign extended to fill the available space." but it is not true. Fix code to match the comment. Also fix casts on each caller to get rid of some warnings. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: Register platform devicesFlorian Fainelli2007-10-29
| | | | | | | | | | This patch separates the platform devices registration for the MTX-1 specific devices: GPIO leds and watchdog. [Minor fixup and formatting change -- Ralf] Signed-off-by: Florian Fainelli <florian.fainelli@telecomint.eu> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add len and addr validation for MAP_FIXED mappings.David Daney2007-10-29
| | | | | | | | | | | | | | | | | | Mmap with MAP_FIXED was not validating the addr and len parameters. This leads to the failure of GCC's gcc.c-torture/execute/loop-2[fg].c testcases when using the o32 ABI on a 64 bit kernel. These testcases try to mmap 65536 bytes at 0x7fff8000 and then access all the memory. In 2.6.18 and 2.6.23.1 (and likely other versions as well) the kernel maps the requested memory, but since half of it is above 0x80000000 a SIGBUS is generated when it is accessed. This patch moves the len validation above the MAP_FIXED processing so that it is always validated. It also adds validation to the addr parameter for MAP_FIXED mappings. Signed-off-by: David Daney <ddaney@avtrex.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IRIX: Fix off-by-one error in signal compat code.Ralf Baechle2007-10-29
| | | | | | Based on original patch by Roel Kluin <12o3l@tiscali.nl>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Replace plat_timer_setup with modern APIs.Ralf Baechle2007-10-29
| | | | | | plat_timer_setup is no longer getting called. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Fix cut'n'paste bug in Sibyte clockevent driver.Ralf Baechle2007-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Make c0_compare_int_usable fasterAtsushi Nemoto2007-10-29
| | | | | | | Try increasingly longer time periods starting of at 0x10 cycles. This should be fast on hardware and work nicely with emulators. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Fix cevt-r4k.c for 64-bit kernelAtsushi Nemoto2007-10-29
| | | | | | | | The expression "(long)(read_c0_count() - cnt)" can never be a negative value on 64-bit kernel. Cast to "int" before comparison. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Delete {sb1250,bcm1480}_steal_irq().Ralf Baechle2007-10-29
| | | | | | | | | They break the timer interrupt initialization and only seem to be a kludge for initialization happening in the wrong order. Further testing done by Thiemo confirms the suspicion that the other invocations also seem to have useless. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] txx9tmr clockevent/clocksource driverAtsushi Nemoto2007-10-29
| | | | | | | | | | | | | | Convert jmr3927_clock_event_device to more generic txx9tmr_clock_event_device which supports one-shot mode. The txx9tmr_clock_event_device can be used for TX49 too if the cp0 timer interrupt was not available. Convert jmr3927_hpt_read to txx9_clocksource driver which does not depends jiffies anymore. The txx9_clocksource itself can be used for TX49, but normally TX49 uses higher precision clocksource_mips. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add mips_hpt_frequency check to mips_clockevent_init().Yoichi Yuasa2007-10-29
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP32: Fixes after interrupt renumbering.Ralf Baechle2007-10-29
| | | | | | And general untangling. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP27: Fix slice logic to work for arbitrary number of slices.Ralf Baechle2007-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SNI: Convert a20r timer to clockevent device.Ralf Baechle2007-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Merge eXcite plat_timer_setup into plat_time_init.Ralf Baechle2007-10-29
| | | | | | | Fixme: At the time of this writing cevt-r4k.c doesn't yet know about how to handle the alternate timer interrupt of the RM9000. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Merge lasat plat_timer_setup into plat_time_init.Ralf Baechle2007-10-29
| | | | | | | | Since the cp0 compare interrupt handler isn't initialized by the time plat_time_init is called don't set IE_IRQ5 anymore, cevt-r4k.c will do that a little later itself. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Remove wrppmc's definition of plat_timer_setup.Ralf Baechle2007-10-29
| | | | | | The only thing it used to do is now done by cevt-r4k.c. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Cause platform definitions of plat_timer_setup to cause error.Ralf Baechle2007-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: Convert from plat_timer_setup to plat_time_init.Ralf Baechle2007-10-29
| | | | | | | The old plat_timer_setup hook is no longer getting called so the Alchemy time initialization was getting skipped. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] vpe: Use p_paddr instead of p_vaddr loader.Ralf Baechle2007-10-29
| | | | | | This subtle difference makes ELF overlays work. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Cleanup random difference between the lmo and kernel.org tree.Ralf Baechle2007-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: set clock before clockevent_delta2ns() in GT641xx.Yoichi Yuasa2007-10-29
| | | | | | | | | clockevent_delta2ns() use the shift and mult value, so clockevent_set_clock() should be called first. Pointed out by Atsushi Nemoto. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Use non-interrupt locks in GT641xx clockevent driverYoichi Yuasa2007-10-29
| | | | | | | | | set_next_event() and set_mode() are always called with interrupt disabled. irqsave and irqrestore are not necessary for spinlock. Pointed out by Atsushi Nemoto. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: micro-optimizatize time code.Ralf Baechle2007-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: Nuke homebrew setup_irq(), it's broken and unnecessary.Ralf Baechle2007-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Allow control over TC assignment to vpe0.Kevin D. Kissell2007-10-29
| | | | | | | | | | | | | | | | | Modify the SMTC initialization code to allow boot-time specification not only of how many VPEs and TCs to use, but also how many TCs out of the allowed pool are to be bound to VPE 0. The new boot option is "vpe0tcs=N", where N is an integer. Using it in combination with the existing options allows arbitrary assignments across the 2 VPEs of a 34K. e.g. "maxtcs=3 vpe0tcs=1" forces VPE0 to have 1 TC, while VPE1 has 2, and "maxtcs=4 vpe0tcs=3" forces VPE0 to have 3 TCs, while VPE1 gets 1. If no vpe0tcs option is specified, the traditional algorithm of evenly dividing TCs between available VPEs, with the odd "slop" going to VPE0, is retained. The reason for doing this is to allow a finer balancing of TCs which can handle I/O interrupts on Malta (those on VPE 0) and those which cannot. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* mips: sg_page() falloutJens Axboe2007-10-23
| | | | Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
* Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2007-10-22
|\ | | | | | | | | | | | | | | | | | | | | | | * 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] time: Make c0_compare_int_usable more bullet proof [MIPS] Kbuild: Use the new cc-cross-prefix feature. [MIPS] Fix include wrapper symbol to something sane. [MIPS] Malta: Delete dead code. [MIPS] time: Add GT641xx timer0 clockevent driver [MIPS] time: SMP-proofing of Sibyte clockevent/clocksource code. [MIPS] time: SMP/NUMA-proofing of IP27 HUB RT timer code. [MIPS] time: Fix calculation in clockevent_set_clock()
| * [MIPS] time: Make c0_compare_int_usable more bullet proofAtsushi Nemoto2007-10-22
| | | | | | | | | | | | | | Use write_c0_compare(read_c0_count()) to clear interrupt. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Kbuild: Use the new cc-cross-prefix feature.Ralf Baechle2007-10-22
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Malta: Delete dead code.Ralf Baechle2007-10-22
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] time: Add GT641xx timer0 clockevent driverYoichi Yuasa2007-10-22
| | | | | | | | | | | | | | | | And make use of it for Cobalt. A few others such as the Malta could make use of it as well. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] time: SMP-proofing of Sibyte clockevent/clocksource code.Ralf Baechle2007-10-22
| | | | | | | | | | | | | | | | | | | | | | The BCM148 has 4 cores but there are also just 4 generic timers available so use the ZBbus cycle counter instead of it. In addition the ZBbus counter also offers a much higher resolution and 64-bit counting so I'm considering a later complete conversion to it once I figure out if all members of the Sibyte SOC family support it - the docs seem to agree but the headers files seem to disagree ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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