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* [MIPS] N32 needs to use the compat version of sys_nfsservctl.Ralf Baechle2007-11-15
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] irq_cpu: use handle_percpu_irq handler to avoid dropping interrupts.Ralf Baechle2007-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This matters to any sort of device that is wired to one of the CPU interrupt pins on an SMP system. Typically the scenario is most easily triggered with the count/compare timer interrupt where the same interrupt number and thus irq_desc is used on each processor. CPU A CPU B do_IRQ() generic_handle_irq() handle_level_irq() spin_lock(desc_lock) set IRQ_INPROGRESS spin_unlock(desc_lock) do_IRQ() generic_handle_irq() handle_level_irq() spin_lock(desc_lock) IRQ_INPROGRESS set => bail out spin_lock(desc_lock) clear IRQ_INPROGRESS spin_unlock(desc_lock) In case of the cp0 compare interrupt this means the interrupt will be acked and not handled or re-armed on CPU b, so there won't be any timer interrupt until the count register wraps around. With kernels 2.6.20 ... 2.6.23 we usually were lucky that things were just working right on VSMP because the count registers are synchronized on bootup so it takes something that disables interrupts for a long time on one processor to trigger this one. For scenarios where an interrupt is multicasted or broadcasted over several CPUs the existing code was safe and the fix will break it. There is no way to know in the interrupt controller code because it is abstracted from the platform code. I think we do not have such a setup currently, so this should be ok. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Fix name of clocksource.Ralf Baechle2007-11-15
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SNI: s/achknowledge/acknowledge/Maciej W. Rozycki2007-11-15
| | | | | Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Makefile: Fix canonical system namesMaciej W. Rozycki2007-11-15
| | | | | | | | The GNU `config.guess' uses "linux-gnu" as the canonical system name. Fix the list of compiler prefixes checked to spell it correctly. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] vpe: handle halting TCs in an errata safe way.Nigel Stephens2007-11-15
| | | | | | | Adds a JR.HB after halting a TC, to ensure that the TC has really halted. only modifies the TCSTATUS register when the TC is safely halted. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Stop timers before programming next even.Ralf Baechle2007-11-15
| | | | | | | | | | | | We have no guarantee by the generic time code that the timer is stopped when the ->next_event method is called. Modifying the Timer Initial Count register while the timer is enabled has UNPREDICTABLE effect according to the BCM1250/BCM1125/BCM1125H User Manual. So stop the timer before reprogramming. This is a paranoia fix; no ill effects have been observed previously. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Increase minimum oneshot timer interval to two ticks.Ralf Baechle2007-11-15
| | | | | | | | | | | | | | | | | For the old minimum of a single tick a value of zero would be programmed into the init value register which in the BCM1250/BCM1125/BCM1125H User Manual in the Timer Special Cases section is documented to have UNPREDICTABLE effect. Observable sympthoms of this bug were hangs of several seconds on the console during bootup and later if both dyntick and highres timer options were activated. In theory contiguous mode of the timers is also affected but in an act of hopeless lack of realism I'll assume nobody will ever configure a KERNEL for HZ > 500kHz but if so I leave that to evolution to sort out. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Lasat: Fix overlap of interrupt number ranges.Yoichi Yuasa2007-11-15
| | | | | | | The range of MIPS_CPU IRQ and the range of LASAT IRQ overlap. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SNI PCIT CPLUS: workaround for b0rked irq wiring of onboard PCI bus 1Thomas Bogendoerfer2007-11-15
| | | | | Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix shadow register support.Ralf Baechle2007-11-15
| | | | | | | | | | | | | Shadow register support would not possibly have worked on multicore systems. The support code for it was also depending not on MIPS R2 but VSMP or SMTC kernels even though it makes perfect sense with UP kernels. SR sets are a scarce resource and the expected usage pattern is that users actually hardcode the register set numbers in their code. So fix the allocator by ditching it. Move the remaining CPU probe bits into the generic CPU probe. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix typo in R3000 TRACE_IRQFLAGS codeAtsushi Nemoto2007-11-15
| | | | | Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Replace use of removed IO_SPACE_BASE with IOADDR.Ralf Baechle2007-11-15
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] iounmap if in vr41xx_pciu_init() pci clock is over 33MHzRoel Kluin2007-11-15
| | | | | | | | | iounmap if pci clock is over 33MHz. Cosmetic because the iomap() in this case is just a bit of address magic. Signed-off-by: Roel Kluin <12o3l@tiscali.nl> Acked-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] BCM1480: Remove duplicate acknowledge of timer interrupt.Ralf Baechle2007-11-15
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: pin timer interrupt to their cores.Ralf Baechle2007-11-15
| | | | | | Or strange things will happen. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Qemu: Add early printk, your friend in a cold night.Ralf Baechle2007-11-15
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Convert reference to mem_map to pfn_to_page().Ralf Baechle2007-11-15
| | | | | | This was crashing the combination of highmem and sparsemem. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: resurrect old cache hack.Ralf Baechle2007-11-15
| | | | | | | | | | | | | | | | | | | The recent switch of the Sibyte SOCs from the processor specific cache managment code in c-sb1.c to c-r4k.c lost this old hack [MIPS] Hack for SB1 cache issues Removing flush_icache_page a while ago broke SB1 which was using an empty flush_data_cache_page function. This glues things well enough so a more efficient but also more intrusive solution can be found later. Signed-Off-By: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> in the hope it was no longer needed. As it turns it still is so resurrect it until there is a better solution. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* mips: undo locking on error path returnsRoel Kluin2007-11-14
| | | | | | | | [akpm@linux-foundation.org: coding-style cleanups] Signed-off-by: Roel Kluin <12o3l@tiscali.nl> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Use i8253.c lock for PC speaker on MIPS, too.Ralf Baechle2007-11-02
| | | | | | | | | | The Jazz machines have to use the PIT timer for dyntick and highresolution kernels. This may break because currently just like i386 used to do MIPS uses two separate spinlocks in the actual PIT code and the PC speaker code. So switch to do it the same that x86 currently does PIT locking. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* [MIPS] Jazz: disable PIT; cleanup R4030 clockeventThomas Bogendoerfer2007-11-02
| | | | | | | | Fix ISA irq acknowledge. Make r4030 clockevent code look like other mips clockevent code. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Bigsur supports highmem.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] mtx-1: Enable -Werror.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] mtx-1: Remove unused mtx1_sys_btn.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Pb1200: Enable -Werror.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SNI: register a02r clockevent; don't use PIT timerThomas Bogendoerfer2007-11-02
| | | | | | | | Register A20R clockevent. Remove PIT timer setup because it doesn't work Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] i8253: Cleanup.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Pb1200: Fix warning.Ralf Baechle2007-11-02
| | | | | | | | arch/mips/au1000/pb1200/irqmap.c:101: warning: ignoring return value of 'request_irq', declared with attribute warn_unused_result And while at it a few coding style cleanups. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Pb1200: Fix warning.Ralf Baechle2007-11-02
| | | | | | arch/mips/au1000/pb1200/board_setup.c:71: warning: unused variable 'pin_func' Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP27: Fix build error.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Excite: Fix build error.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Split and move clock code.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Fixes for oneshot timer mode.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Remove blank line.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Swarm: Fix build failureThiemo Seufer2007-11-02
| | | | | Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Code cleanupsAtsushi Nemoto2007-11-02
| | | | | | | | | | | | | * Do not include unnecessary headers. * Do not mention time.README. * Do not mention mips_timer_ack. * Make clocksource_mips static. It is now dedicated to c0_timer. * Initialize clocksource_mips.read statically. * Remove null_hpt_read. * Remove an argument of plat_timer_setup. It is just a placeholder. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Remove now unused local_timer_interrupt.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP32: Fix address of 2nd serial interface.Ralf Baechle2007-11-02
| | | | | | Found by Giuseppe Sacco <giuseppe@eppesuigoccas.homedns.org>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SB1250: Use the right irqaction for the timer interrupt.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SB1250: Remove stray assignment of cpumask.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Fix names of the clockevent devices.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Build fixes / dead code removal.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] tb0219: Update copyright message.Ralf Baechle2007-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] MT: Fix bug in multithreaded kernels.Ralf Baechle2007-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When GDB writes a breakpoint into address area of inferior process the kernel needs to invalidate the modified memory in the inferior which is done by calling flush_cache_page which in turns calls r4k_flush_cache_page and local_r4k_flush_cache_page for VSMP or SMTC kernel via r4k_on_each_cpu(). As the VSMP and SMTC SMP kernels for 34K are running on a single shared caches it is possible to get away without interprocessor function calls. This optimization is implemented in r4k_on_each_cpu, so local_r4k_flush_cache_page is only ever called on the local CPU. This is where the following code in local_r4k_flush_cache_page() strikes: /* * If ownes no valid ASID yet, cannot possibly have gotten * this page into the cache. */ if (cpu_context(smp_processor_id(), mm) == 0) return; On VSMP and SMTC had a function of cpu_context() for each CPU(TC). So in case another CPU than the CPU executing local_r4k_cache_flush_page has not accessed the mm but one of the other CPUs has there may be data to be flushed in the cache yet local_r4k_cache_flush_page will falsely return leaving the I-cache inconsistent for the breakpoint. While the issue was discovered with GDB it also exists in local_r4k_flush_cache_range() and local_r4k_flush_cache(). Fixed by introducing a new function has_valid_asid which on MT kernels returns true if a mm is active on any processor in the system. This is relativly expensive since for memory acccesses in that loop cache misses have to be assumed but it seems the most viable solution for 2.6.23 and older -stable kernels. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: Remove CONFIG_TS_AU1X00_ADS7846 from defconfigs.Ralf Baechle2007-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Author: Ralf Baechle <ralf@linux-mips.org>Ralf Baechle2007-10-29
| | | | | | [MIPS] MSP71xx: Fix bitrot. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] sb1250: Enable GenBus IDE in defconfig.Maciej W. Rozycki2007-10-29
| | | | | | | Enable the onboard GenBus IDE interface in the default configuration. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] vmlinux.ld.S: correctly indent .data sectionFranck Bui-Huu2007-10-29
| | | | | Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] c-r3k: Implement flush_cache_range()Maciej W. Rozycki2007-10-29
| | | | | | | | | | | | | | Contrary to the belief of some, the R3000 and related processors did have caches, both a data and an instruction cache. Here is an implementation of r3k_flush_cache_page(), which is the processor-specific back-end for flush_cache_range(), done according to the spec in Documentation/cachetlb.txt. While at it, remove an unused local function: get_phys_page(), do some trivial formatting fixes and modernise debugging facilities. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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