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* [MIPS] Ensure that ST0_FR is never set on a 32 bit kernelChris Dearman2007-12-14
| | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Delete weak definition of plat_time_init() due to gcc bug.Ralf Baechle2007-12-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Frank Rowand <frank.rowand@am.sony.com> reports: > In linux-2.6.24-rc4 the Toshiba RBTX4927 hangs on boot. > > The cause is that plat_time_init() from arch/mips/tx4927/common/ > tx4927_setup.c does not override the __weak plat_time_init() from > arch/mips/kernel/time.c. This is due to a compiler bug in gcc 4.1.1. The > bug is reported to not exist in earlier versions of gcc, and to be fixed in > 4.1.2. The problem is that the __weak plat_time_init() is empty and thus > gets optimized out of existence (thus the linker is never given the option > to replace the __weak function). [ He meant the call to plat_time_init() from time_init() gets optimized away ] > For more info on the gcc bug see > > http://gcc.gnu.org/bugzilla/show_bug.cgi?id=27781 > > The attached patch is one workaround. Another possible workaround [ His patch adds -fno-unit-at-a-time for time.c ] > would be to change the __weak plat_time_init() to be a non-empty > function. The __weak definition of plat_time_init was only ever meant to be a migration helper to keep platforms that don't have a plat_time_init compiling. A few greps says that all platforms now supply their own plat_time_init() so the weak definition is no longer needed. So I instead delete it. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] PCI: Make pcibios_fixup_device_resources ignore legacy resources.Ralf Baechle2007-12-14
| | | | | | | | There might be other reasons why a resource might be marked as fixed such as a PCI UART holding the system console but until we use IORESOURCE_PCI_FIXED that way also this will work. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Atlas, Malta: Don't free firmware memory on free_initmem.Ralf Baechle2007-12-14
| | | | | | | A proper fix for this needs to turn a few MIPS-generic bits which I don't want at this stage. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: fix off by two error in __fixup_bigphys_addr()Sergei Shtylyov2007-12-14
| | | | | | | | | the PCI specific code in this function doesn't check for the address range being under the upper bound of the PCI memory window correctly -- fix this, somewhat beautifying the code around the check, while at it... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: fix PCI resource conflictSergei Shtylyov2007-12-14
| | | | | | | | | ... by getting the PCI resources back into the 32-bit range -- there's no need therefore for CONFIG_RESOURCES_64BIT either. This makes Alchemy PCI work again while currently the kernel skips the bus scan. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Set up Cobalt's mips_hpt_frequencyYoichi Yuasa2007-12-14
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Malta: Enable tickless and highres timers.Ralf Baechle2007-12-08
| | | | | | | | Most Malta use an FPGA CPU card which rarely is good for more than 40MHz. So the performance penalta of the regular timer interrupt, especially for the VSMP kernel model is significant, even at a mere 100Hz. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Bigsur: Enable tickless and and highres timers.Ralf Baechle2007-12-08
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* qemu: do not enable IP7 blindlyAtsushi Nemoto2007-12-08
| | | | | | | IP7 will be enabled automatically in mips_clockevent_init(), if available. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Don't byteswap writes to display when running bigendianChris Dearman2007-12-08
| | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2007-12-06
|\ | | | | | | | | | | | | | | * 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] Oprofile: Fix computation of number of counters. [MIPS] Alchemy: fix IRQ bases [MIPS] Alchemy: replace ffs() with __ffs() [MIPS] BCM1480: Fix interrupt routing, take 2.
| * [MIPS] Oprofile: Fix computation of number of counters.Ralf Baechle2007-12-06
| | | | | | | | | | | | | | VSMP kernels will split the available performance counters between the two processors / cores. But don't do this when we're not on a VSMP system ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Alchemy: fix IRQ basesSergei Shtylyov2007-12-06
| | | | | | | | | | | | | | | | | | Do what the commits commits f3e8d1da389fe2e514e31f6e93c690c8e1243849 and 9d360ab4a7568a8d177280f651a8a772ae52b9b9 failed to achieve -- actually convert the Alchemy code to irq_cpu. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Alchemy: replace ffs() with __ffs()Sergei Shtylyov2007-12-06
| | | | | | | | | | | | | | | | | | | | Fix havoc wrought by commit 56f621c7f6f735311eed3f36858b402013023c18 -- au_ffs() and ffs() are equivalent, that patch should have just replaced one with another. Now replace ffs() with __ffs() which returns an unbiased bit number. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] BCM1480: Fix interrupt routing, take 2.Ralf Baechle2007-12-06
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | Fix oprofile configuration breakageRalf Baechle2007-12-06
|/ | | | | | | | | | | | | | The cleanup 09cadedbdc01f1a4bea1f427d4fb4642eaa19da9 broke the oprofile configuration for MIPS by allowing oprofile support to be built for kernel models where oprofile doesn't have a chance in hell to work. Just a dependecy list on a number of architectures is - surprise - broken and should as per past discussions probably in most considered to be broken in most cases. So I introduce a dependency for the oprofile configuration on ARCH_SUPPORTS_OPROFILE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* [MIPS] BCM1480: Fix interrupt routing.Ralf Baechle2007-12-03
| | | | | | | The old code did did only work as long as CFE and the kernel were using the same interrupt numbering ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix build.Ralf Baechle2007-11-30
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* IP22ZILOG: fix lockup and sysrqThomas Bogendoerfer2007-11-29
| | | | | | | | | | | | - fix lockup when switching from early console to real console - make sysrq reliable - fix panic, if sysrq is issued before console is opened Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* [MIPS] vpe: Add missing "space"Joe Perches2007-11-26
| | | | | Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Compliment va_start() with va_end().Richard Knutsson2007-11-26
| | | | | Signed-off-by: Richard Knutsson <ricknu-0@student.ltu.se> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP22: Fix broken eeprom access by using __raw_readl/__raw_writelThomas Bogendoerfer2007-11-26
| | | | | Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP22: Fix broken EISA interrupt setup by switching to generic i8259Thomas Bogendoerfer2007-11-26
| | | | | Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] 64-bit Sibyte kernels need DMA32.Ralf Baechle2007-11-26
| | | | | | | | | | | | Sibyte SOCs only have 32-bit PCI. Due to the sparse use of the address space only the first 1GB of memory is mapped at physical addresses below 1GB. If a system has more than 1GB of memory 32-bit DMA will not be able to reach all of it. For now this patch is good enough to keep Sibyte users happy but it seems eventually something like swiotlb will be needed for Sibyte. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Only build r4k clocksource for systems that work ok with it.Ralf Baechle2007-11-26
| | | | | | | | | | In particular as-is it's not suited for multicore and mutiprocessors systems where there is on guarantee that the counter are synchronized or running from the same clock at all. This broke Sibyte and probably others since the "[MIPS] Handle R4000/R4400 mfc0 from count register." commit. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Handle R4000/R4400 mfc0 from count register.Ralf Baechle2007-11-26
| | | | | | | | | | | | | | | | | | | | | The R4000 and R4400 have an errata where if the cp0 count register is read in the exact moment when it matches the compare register no interrupt will be generated. This bug may be triggered if the cp0 count register is being used as clocksource and the compare interrupt as clockevent. So a simple workaround is to avoid using the compare for both facilities on the affected CPUs. This is different from the workaround suggested in the old errata documents; at some opportunity probably the official version should be implemented and tested. Another thing to find out is which processor versions exactly are affected. I only have errata documents upto R4400 V3.0 available so for the moment the code treats all R4000 and R4400 as broken. This is potencially a problem for some machines that have no other decent clocksource available; this workaround will cause them to fall back to another clocksource, worst case the "jiffies" source.
* [MIPS] IP32: More interrupt renumbering fixes.Ralf Baechle2007-11-26
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: MIPSsim's plat_time_init doesn't need to be irq safe.Ralf Baechle2007-11-26
| | | | | | It's running early during the bootup process so interrupts are still off. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Fix negated condition in cevt-r4k driver.Ralf Baechle2007-11-26
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] N32 needs to use the compat version of sys_nfsservctl.Ralf Baechle2007-11-15
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] irq_cpu: use handle_percpu_irq handler to avoid dropping interrupts.Ralf Baechle2007-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This matters to any sort of device that is wired to one of the CPU interrupt pins on an SMP system. Typically the scenario is most easily triggered with the count/compare timer interrupt where the same interrupt number and thus irq_desc is used on each processor. CPU A CPU B do_IRQ() generic_handle_irq() handle_level_irq() spin_lock(desc_lock) set IRQ_INPROGRESS spin_unlock(desc_lock) do_IRQ() generic_handle_irq() handle_level_irq() spin_lock(desc_lock) IRQ_INPROGRESS set => bail out spin_lock(desc_lock) clear IRQ_INPROGRESS spin_unlock(desc_lock) In case of the cp0 compare interrupt this means the interrupt will be acked and not handled or re-armed on CPU b, so there won't be any timer interrupt until the count register wraps around. With kernels 2.6.20 ... 2.6.23 we usually were lucky that things were just working right on VSMP because the count registers are synchronized on bootup so it takes something that disables interrupts for a long time on one processor to trigger this one. For scenarios where an interrupt is multicasted or broadcasted over several CPUs the existing code was safe and the fix will break it. There is no way to know in the interrupt controller code because it is abstracted from the platform code. I think we do not have such a setup currently, so this should be ok. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Fix name of clocksource.Ralf Baechle2007-11-15
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SNI: s/achknowledge/acknowledge/Maciej W. Rozycki2007-11-15
| | | | | Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Makefile: Fix canonical system namesMaciej W. Rozycki2007-11-15
| | | | | | | | The GNU `config.guess' uses "linux-gnu" as the canonical system name. Fix the list of compiler prefixes checked to spell it correctly. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] vpe: handle halting TCs in an errata safe way.Nigel Stephens2007-11-15
| | | | | | | Adds a JR.HB after halting a TC, to ensure that the TC has really halted. only modifies the TCSTATUS register when the TC is safely halted. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Stop timers before programming next even.Ralf Baechle2007-11-15
| | | | | | | | | | | | We have no guarantee by the generic time code that the timer is stopped when the ->next_event method is called. Modifying the Timer Initial Count register while the timer is enabled has UNPREDICTABLE effect according to the BCM1250/BCM1125/BCM1125H User Manual. So stop the timer before reprogramming. This is a paranoia fix; no ill effects have been observed previously. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Increase minimum oneshot timer interval to two ticks.Ralf Baechle2007-11-15
| | | | | | | | | | | | | | | | | For the old minimum of a single tick a value of zero would be programmed into the init value register which in the BCM1250/BCM1125/BCM1125H User Manual in the Timer Special Cases section is documented to have UNPREDICTABLE effect. Observable sympthoms of this bug were hangs of several seconds on the console during bootup and later if both dyntick and highres timer options were activated. In theory contiguous mode of the timers is also affected but in an act of hopeless lack of realism I'll assume nobody will ever configure a KERNEL for HZ > 500kHz but if so I leave that to evolution to sort out. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Lasat: Fix overlap of interrupt number ranges.Yoichi Yuasa2007-11-15
| | | | | | | The range of MIPS_CPU IRQ and the range of LASAT IRQ overlap. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SNI PCIT CPLUS: workaround for b0rked irq wiring of onboard PCI bus 1Thomas Bogendoerfer2007-11-15
| | | | | Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix shadow register support.Ralf Baechle2007-11-15
| | | | | | | | | | | | | Shadow register support would not possibly have worked on multicore systems. The support code for it was also depending not on MIPS R2 but VSMP or SMTC kernels even though it makes perfect sense with UP kernels. SR sets are a scarce resource and the expected usage pattern is that users actually hardcode the register set numbers in their code. So fix the allocator by ditching it. Move the remaining CPU probe bits into the generic CPU probe. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix typo in R3000 TRACE_IRQFLAGS codeAtsushi Nemoto2007-11-15
| | | | | Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Replace use of removed IO_SPACE_BASE with IOADDR.Ralf Baechle2007-11-15
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] iounmap if in vr41xx_pciu_init() pci clock is over 33MHzRoel Kluin2007-11-15
| | | | | | | | | iounmap if pci clock is over 33MHz. Cosmetic because the iomap() in this case is just a bit of address magic. Signed-off-by: Roel Kluin <12o3l@tiscali.nl> Acked-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] BCM1480: Remove duplicate acknowledge of timer interrupt.Ralf Baechle2007-11-15
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: pin timer interrupt to their cores.Ralf Baechle2007-11-15
| | | | | | Or strange things will happen. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Qemu: Add early printk, your friend in a cold night.Ralf Baechle2007-11-15
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Convert reference to mem_map to pfn_to_page().Ralf Baechle2007-11-15
| | | | | | This was crashing the combination of highmem and sparsemem. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: resurrect old cache hack.Ralf Baechle2007-11-15
| | | | | | | | | | | | | | | | | | | The recent switch of the Sibyte SOCs from the processor specific cache managment code in c-sb1.c to c-r4k.c lost this old hack [MIPS] Hack for SB1 cache issues Removing flush_icache_page a while ago broke SB1 which was using an empty flush_data_cache_page function. This glues things well enough so a more efficient but also more intrusive solution can be found later. Signed-Off-By: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> in the hope it was no longer needed. As it turns it still is so resurrect it until there is a better solution. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* mips: undo locking on error path returnsRoel Kluin2007-11-14
| | | | | | | | [akpm@linux-foundation.org: coding-style cleanups] Signed-off-by: Roel Kluin <12o3l@tiscali.nl> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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