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* cpu-hotplug: replace lock_cpu_hotplug() with get_online_cpus()Gautham R Shenoy2008-01-25
| | | | | | | | | | | | | | | | | Replace all lock_cpu_hotplug/unlock_cpu_hotplug from the kernel and use get_online_cpus and put_online_cpus instead as it highlights the refcount semantics in these operations. The new API guarantees protection against the cpu-hotplug operation, but it doesn't guarantee serialized access to any of the local data structures. Hence the changes needs to be reviewed. In case of pseries_add_processor/pseries_remove_processor, use cpu_maps_update_begin()/cpu_maps_update_done() as we're modifying the cpu_present_map there. Signed-off-by: Gautham R Shenoy <ego@in.ibm.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* Driver core: change sysdev classes to use dynamic kobject namesKay Sievers2008-01-24
| | | | | | | | | | All kobjects require a dynamically allocated name now. We no longer need to keep track if the name is statically assigned, we can just unconditionally free() all kobject names on cleanup. Signed-off-by: Kay Sievers <kay.sievers@vrfy.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* tc35815: Use irq number for tc35815-mac platform device idAtsushi Nemoto2008-01-21
| | | | | | | | | | The tc35815-mac platform device used a pci bus number and a devfn to identify its target device, but the pci bus number may vary if some bus-bridges are found. Use irq number which is be unique for embedded controllers. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Malta: Fix reading the PCI clock frequency on big-endianDmitri Vorobiev2008-01-21
| | | | | | | | | | | | | | | | | | The JMPRS register on Malta boards keeps a 32-bit CPU-endian value. The readw() function assumes that the value it reads is a little-endian 16-bit number. Therefore, using readw() to obtain the value of the JMPRS register is a mistake. This error leads to incorrect reading of the PCI clock frequency on big-endian during board start-up. Change readw() to __raw_readl(). This was tested by injecting a call to printk() and verifying that the value of the jmpr variable was consistent with current setting of the JP4 "PCI CLK" jumper. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2008-01-15
|\ | | | | | | | | | | | | | | * 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] Cacheops.h: Fix typo. [MIPS] Cobalt: Qube1 has no serial port so don't use it [MIPS] Cobalt: Fix ethernet interrupts for RaQ1 [MIPS] Kconfig fixes for BCM47XX platform
| * [MIPS] Cobalt: Qube1 has no serial port so don't use itThomas Bogendoerfer2008-01-14
| | | | | | | | | | | | | | | | | | | | Because Qube1 doesn't have a serial chip waiting for transmit fifo empty takes forever, which isn't a good idea. No prom_putchar/early console for Qube1 fixes this. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Acked-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Cobalt: Fix ethernet interrupts for RaQ1Thomas Bogendoerfer2008-01-14
| | | | | | | | | | | | | | RAQ1 uses the same interrupt routing as Qube2. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Kconfig fixes for BCM47XX platformAurelien Jarno2008-01-14
| | | | | | | | | | | | | | | | | | | | | | | | The patch below fixes two problems for Kconfig on the BCM47xx platform: - arch/mips/bcm47xx/gpio.c uses ssb_extif_* functions. Selecting SSB_DRIVER_EXTIF makes sure those functions are available. - arch/mips/pci/pci.c needs, when enabled, platform specific functions, which are defined when SSB_PCICORE_HOSTMODE is enabled. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | [MIPS] Replace 40c7869b693b18412491fdcff64682215b739f9e kludgeAtsushi Nemoto2008-01-11
| | | | | | | | | | Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | [MIPS] Lasat: Fix built in separate object directory.WANG Cong2008-01-11
| | | | | | | | | | | | | | | | Signed-off-by: WANG Cong <xiyou.wangcong@gmail.com> [Ralf: The LDSCRIPT script needed fixing, too] Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | [MIPS] Malta: Fix software reset on big endianDmitri Vorobiev2008-01-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I noticed that the commit f197465384bf7ef1af184c2ed1a4e268911a91e3 (MIPS Tech: Get rid of volatile in core code) broke the software reset functionality for MIPS Malta boards in big-endian mode. According to the MIPS Malta board user's manual, writing the magic 32-bit GORESET value into the SOFTRES register initiates board soft reset. My experimentation has shown that the endianness of the GORESET integer should thereby be the same as the endianness, which has been set for the CPU itself. The writew() function used to write the magic value in the code introduced by the commit mentioned above, however, swaps bytes for big-endian kernels and transfers 16 bits instead of 32. The patch below replaces the writew() function by the __raw_writel() routine, which leaves the byte order intact and transfers the whole MIPS machine word. Trivial code cleanup (replacing spaces by a tab and cutting oversized lines to make checkpatch.pl happy) is also included. The patch was tested using a Malta evaluation board running in both BE and LE modes. For both modes, software reset was fully functional after the change. P.S. I suspect that the same commit broke the "standby" functionality for MIPS Atlas boards. However, I did not touch the Atlas code as I don't have such board at my disposal and also because the linux-mips.org Web site claims that Atlas support is scheduled for removal. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | [MIPS] pnx8xxx: move to clocksourceVitaly Wool2008-01-11
| | | | | | | | | | | | | | | | This patch converts PNX8XXX system timer to clocksource restoring PNX8550 support back to live. Signed-off-by: Vitaly Wool <vitalywool@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | [MIPS] Wrong CONFIG option prevents setup of DMA zone.Thomas Bogendoerfer2008-01-11
|/ | | | | Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix CONFIG_BOOT_RAW.Ralf Baechle2008-01-07
| | | | | | | This was broken by 017e3a492683b32d17dcd1b13b279745cc656073 (lmo) / 396a2ae08e5080b140330645743ab2567f6bc426 (kernel.org). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Assume R4000/R4400 newer than 3.0 don't have the mfc0 count bugThomas Bogendoerfer2008-01-07
| | | | | | | | This seems as reasonable assumption and gets some SNI machines to work which currently must rely on the cp0 counter as clocksource. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix IP32 breakageThomas Bogendoerfer2008-01-07
| | | | | | | | | | | | | - suppress master aborts during config read - set io_map_base - only fixup end of iomem resource to avoid failing request_resource in serial driver - killed useless setting of crime_int bit, which caused wrong interrupts - use physcial address for serial port platform device and let 8250 driver do the ioremap Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: Fix use of __init code bug exposed by modpost warningSergei Shtylyov2008-01-07
| | | | | | | | | | | | | | | WARNING: vmlinux.o(.text+0x1ca608): Section mismatch: reference to .init.text: add_wired_entry (between 'config_access' and 'config_read') by refactoring the code calling add_wired_entry() from config_access() to a separate function which is called from aau1x_pci_setup(). While at it: - make some unnecassarily global variables 'static'; - fix the letter case, whitespace, etc. in the comments... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Move inclusing of kernel/time/Kconfig menu to appropriate placeAtsushi Nemoto2008-01-07
| | | | | | | | CONFIG_NO_HZ, CONFIG_HIGH_RES_TIMERS should be selected in "Kernel type" menu, not in "CPU selection" menu. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Ensure that ST0_FR is never set on a 32 bit kernelChris Dearman2007-12-14
| | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Delete weak definition of plat_time_init() due to gcc bug.Ralf Baechle2007-12-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Frank Rowand <frank.rowand@am.sony.com> reports: > In linux-2.6.24-rc4 the Toshiba RBTX4927 hangs on boot. > > The cause is that plat_time_init() from arch/mips/tx4927/common/ > tx4927_setup.c does not override the __weak plat_time_init() from > arch/mips/kernel/time.c. This is due to a compiler bug in gcc 4.1.1. The > bug is reported to not exist in earlier versions of gcc, and to be fixed in > 4.1.2. The problem is that the __weak plat_time_init() is empty and thus > gets optimized out of existence (thus the linker is never given the option > to replace the __weak function). [ He meant the call to plat_time_init() from time_init() gets optimized away ] > For more info on the gcc bug see > > http://gcc.gnu.org/bugzilla/show_bug.cgi?id=27781 > > The attached patch is one workaround. Another possible workaround [ His patch adds -fno-unit-at-a-time for time.c ] > would be to change the __weak plat_time_init() to be a non-empty > function. The __weak definition of plat_time_init was only ever meant to be a migration helper to keep platforms that don't have a plat_time_init compiling. A few greps says that all platforms now supply their own plat_time_init() so the weak definition is no longer needed. So I instead delete it. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] PCI: Make pcibios_fixup_device_resources ignore legacy resources.Ralf Baechle2007-12-14
| | | | | | | | There might be other reasons why a resource might be marked as fixed such as a PCI UART holding the system console but until we use IORESOURCE_PCI_FIXED that way also this will work. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Atlas, Malta: Don't free firmware memory on free_initmem.Ralf Baechle2007-12-14
| | | | | | | A proper fix for this needs to turn a few MIPS-generic bits which I don't want at this stage. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: fix off by two error in __fixup_bigphys_addr()Sergei Shtylyov2007-12-14
| | | | | | | | | the PCI specific code in this function doesn't check for the address range being under the upper bound of the PCI memory window correctly -- fix this, somewhat beautifying the code around the check, while at it... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: fix PCI resource conflictSergei Shtylyov2007-12-14
| | | | | | | | | ... by getting the PCI resources back into the 32-bit range -- there's no need therefore for CONFIG_RESOURCES_64BIT either. This makes Alchemy PCI work again while currently the kernel skips the bus scan. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Set up Cobalt's mips_hpt_frequencyYoichi Yuasa2007-12-14
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Malta: Enable tickless and highres timers.Ralf Baechle2007-12-08
| | | | | | | | Most Malta use an FPGA CPU card which rarely is good for more than 40MHz. So the performance penalta of the regular timer interrupt, especially for the VSMP kernel model is significant, even at a mere 100Hz. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Bigsur: Enable tickless and and highres timers.Ralf Baechle2007-12-08
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* qemu: do not enable IP7 blindlyAtsushi Nemoto2007-12-08
| | | | | | | IP7 will be enabled automatically in mips_clockevent_init(), if available. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Don't byteswap writes to display when running bigendianChris Dearman2007-12-08
| | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2007-12-06
|\ | | | | | | | | | | | | | | * 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] Oprofile: Fix computation of number of counters. [MIPS] Alchemy: fix IRQ bases [MIPS] Alchemy: replace ffs() with __ffs() [MIPS] BCM1480: Fix interrupt routing, take 2.
| * [MIPS] Oprofile: Fix computation of number of counters.Ralf Baechle2007-12-06
| | | | | | | | | | | | | | VSMP kernels will split the available performance counters between the two processors / cores. But don't do this when we're not on a VSMP system ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Alchemy: fix IRQ basesSergei Shtylyov2007-12-06
| | | | | | | | | | | | | | | | | | Do what the commits commits f3e8d1da389fe2e514e31f6e93c690c8e1243849 and 9d360ab4a7568a8d177280f651a8a772ae52b9b9 failed to achieve -- actually convert the Alchemy code to irq_cpu. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] Alchemy: replace ffs() with __ffs()Sergei Shtylyov2007-12-06
| | | | | | | | | | | | | | | | | | | | Fix havoc wrought by commit 56f621c7f6f735311eed3f36858b402013023c18 -- au_ffs() and ffs() are equivalent, that patch should have just replaced one with another. Now replace ffs() with __ffs() which returns an unbiased bit number. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * [MIPS] BCM1480: Fix interrupt routing, take 2.Ralf Baechle2007-12-06
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | Fix oprofile configuration breakageRalf Baechle2007-12-06
|/ | | | | | | | | | | | | | The cleanup 09cadedbdc01f1a4bea1f427d4fb4642eaa19da9 broke the oprofile configuration for MIPS by allowing oprofile support to be built for kernel models where oprofile doesn't have a chance in hell to work. Just a dependecy list on a number of architectures is - surprise - broken and should as per past discussions probably in most considered to be broken in most cases. So I introduce a dependency for the oprofile configuration on ARCH_SUPPORTS_OPROFILE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* [MIPS] BCM1480: Fix interrupt routing.Ralf Baechle2007-12-03
| | | | | | | The old code did did only work as long as CFE and the kernel were using the same interrupt numbering ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix build.Ralf Baechle2007-11-30
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* IP22ZILOG: fix lockup and sysrqThomas Bogendoerfer2007-11-29
| | | | | | | | | | | | - fix lockup when switching from early console to real console - make sysrq reliable - fix panic, if sysrq is issued before console is opened Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* [MIPS] vpe: Add missing "space"Joe Perches2007-11-26
| | | | | Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Compliment va_start() with va_end().Richard Knutsson2007-11-26
| | | | | Signed-off-by: Richard Knutsson <ricknu-0@student.ltu.se> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP22: Fix broken eeprom access by using __raw_readl/__raw_writelThomas Bogendoerfer2007-11-26
| | | | | Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IP22: Fix broken EISA interrupt setup by switching to generic i8259Thomas Bogendoerfer2007-11-26
| | | | | Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] 64-bit Sibyte kernels need DMA32.Ralf Baechle2007-11-26
| | | | | | | | | | | | Sibyte SOCs only have 32-bit PCI. Due to the sparse use of the address space only the first 1GB of memory is mapped at physical addresses below 1GB. If a system has more than 1GB of memory 32-bit DMA will not be able to reach all of it. For now this patch is good enough to keep Sibyte users happy but it seems eventually something like swiotlb will be needed for Sibyte. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Only build r4k clocksource for systems that work ok with it.Ralf Baechle2007-11-26
| | | | | | | | | | In particular as-is it's not suited for multicore and mutiprocessors systems where there is on guarantee that the counter are synchronized or running from the same clock at all. This broke Sibyte and probably others since the "[MIPS] Handle R4000/R4400 mfc0 from count register." commit. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Handle R4000/R4400 mfc0 from count register.Ralf Baechle2007-11-26
| | | | | | | | | | | | | | | | | | | | | The R4000 and R4400 have an errata where if the cp0 count register is read in the exact moment when it matches the compare register no interrupt will be generated. This bug may be triggered if the cp0 count register is being used as clocksource and the compare interrupt as clockevent. So a simple workaround is to avoid using the compare for both facilities on the affected CPUs. This is different from the workaround suggested in the old errata documents; at some opportunity probably the official version should be implemented and tested. Another thing to find out is which processor versions exactly are affected. I only have errata documents upto R4400 V3.0 available so for the moment the code treats all R4000 and R4400 as broken. This is potencially a problem for some machines that have no other decent clocksource available; this workaround will cause them to fall back to another clocksource, worst case the "jiffies" source.
* [MIPS] IP32: More interrupt renumbering fixes.Ralf Baechle2007-11-26
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: MIPSsim's plat_time_init doesn't need to be irq safe.Ralf Baechle2007-11-26
| | | | | | It's running early during the bootup process so interrupts are still off. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: Fix negated condition in cevt-r4k driver.Ralf Baechle2007-11-26
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] N32 needs to use the compat version of sys_nfsservctl.Ralf Baechle2007-11-15
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] irq_cpu: use handle_percpu_irq handler to avoid dropping interrupts.Ralf Baechle2007-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This matters to any sort of device that is wired to one of the CPU interrupt pins on an SMP system. Typically the scenario is most easily triggered with the count/compare timer interrupt where the same interrupt number and thus irq_desc is used on each processor. CPU A CPU B do_IRQ() generic_handle_irq() handle_level_irq() spin_lock(desc_lock) set IRQ_INPROGRESS spin_unlock(desc_lock) do_IRQ() generic_handle_irq() handle_level_irq() spin_lock(desc_lock) IRQ_INPROGRESS set => bail out spin_lock(desc_lock) clear IRQ_INPROGRESS spin_unlock(desc_lock) In case of the cp0 compare interrupt this means the interrupt will be acked and not handled or re-armed on CPU b, so there won't be any timer interrupt until the count register wraps around. With kernels 2.6.20 ... 2.6.23 we usually were lucky that things were just working right on VSMP because the count registers are synchronized on bootup so it takes something that disables interrupts for a long time on one processor to trigger this one. For scenarios where an interrupt is multicasted or broadcasted over several CPUs the existing code was safe and the fix will break it. There is no way to know in the interrupt controller code because it is abstracted from the platform code. I think we do not have such a setup currently, so this should be ok. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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