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* MIPS: Alchemy: Simplify DMA channel allocation code.Ralf Baechle2010-02-27
| | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Manuel Lauss <manuel.lauss@googlemail.com>
* MIPS: Yosemite: Convert SMP startup lock to arch spinlock.Ralf Baechle2010-02-27
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Remove time_lock.Ralf Baechle2010-02-27
| | | | | | | | The sole user is au1xxx_calc_clock() which is only used in early bootup where the is no paralellism thus no race condition to protect against. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Manuel Lauss <manuel.lauss@googlemail.com>
* MIPS: DEC: Convert KN01 lock to raw spinlock.Ralf Baechle2010-02-27
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63xx: Convert timer locks to raw spinlocks.Ralf Baechle2010-02-27
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: PowerTV: Convert IRQ controller lock to raw spinlock.Ralf Baechle2010-02-27
| | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: David VomLehn <dvomlehn@cisco.com>
* MIPS: Malta: Convert IRQ controller lock to raw spinlock.Ralf Baechle2010-02-27
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: SB1480: Convert IRQ controller lock to raw spinlock.Ralf Baechle2010-02-27
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: SB1250: Convert IRQ controller lock to raw spinlock.Ralf Baechle2010-02-27
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: GT641xx: Convert IRQ controller lock to raw spinlock.Ralf Baechle2010-02-27
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Jazz: Convert irq controller lock to raw spinlock.Ralf Baechle2010-02-27
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Make various locks static.Ralf Baechle2010-02-27
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Octeon: Do proper acknowledgment of CIU timer interrupts.David Daney2010-02-27
| | | | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org To: netdev@vger.kernel.org To: gregkh@suse.de Patchwork: http://patchwork.linux-mips.org/patch/967/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Use generic ucontext.hYoichi Yuasa2010-02-27
| | | | | | | Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/959/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Use generic serial.hYoichi Yuasa2010-02-27
| | | | | | | Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/960/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Use generic parport.hYoichi Yuasa2010-02-27
| | | | | | | Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/958/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Use generic current.hYoichi Yuasa2010-02-27
| | | | | | | Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/957/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUsDavid Daney2010-02-27
| | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/955/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Give Octeon+ CPUs their own cputype.David Daney2010-02-27
| | | | | | | | | | This allows us to treat them differently at runtime. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/951/ Patchwork: http://patchwork.linux-mips.org/patch/987/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Implement Read Inhibit/eXecute InhibitDavid Daney2010-02-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SmartMIPS ASE specifies how Read Inhibit (RI) and eXecute Inhibit (XI) bits in the page tables work. The upper two bits of EntryLo{0,1} are RI and XI when the feature is enabled in the PageGrain register. SmartMIPS only covers 32-bit systems. Cavium Octeon+ extends this to 64-bit systems by continuing to place the RI and XI bits in the top of EntryLo even when EntryLo is 64-bits wide. Because we need to carry the RI and XI bits in the PTE, the layout of the PTE is changed. There is a two instruction overhead in the TLB refill hot path to get the EntryLo bits into the proper position. Also the TLB load exception has to probe the TLB to check if RI or XI caused the exception. Also of note is that the layout of the PTE bits is done at compile and runtime rather than statically. In the 32-bit case this allows for the same number of PFN bits as before the patch as the _PAGE_HUGE is not supported in 32-bit kernels (we have _PAGE_NO_EXEC and _PAGE_NO_READ instead of _PAGE_READ and _PAGE_HUGE). The patch is tested on Cavium Octeon+, but should also work on 32-bit systems with the Smart-MIPS ASE. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/952/ Patchwork: http://patchwork.linux-mips.org/patch/956/ Patchwork: http://patchwork.linux-mips.org/patch/962/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add TLBR and ROTR to uasm.David Daney2010-02-27
| | | | | | | | | | The soon to follow Read Inhibit/eXecute Inhibit patch needs TLBR and ROTR support in uasm. We also add a UASM_i_ROTR macro. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/953/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add accessor functions and bit definitions for c0_PageGrainDavid Daney2010-02-27
| | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/950/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Use 64-bit stores to c0_entrylo on 64-bit kernels.David Daney2010-02-27
| | | | | | | | | | | 64-bit CPUs have 64-bit c0_entrylo{0,1} registers. We should use the 64-bit dmtc0 instruction to set them. This becomes important if we want to set the RI and XI bits present in some processors. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/954/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove trailing space in messagesFrans Pop2010-02-27
| | | | | | | | Signed-off-by: Frans Pop <elendil@planet.nl> To: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/946/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Make the debugging of compressed kernel configurableWu Zhangjin2010-02-27
| | | | | | | | | | | | | | This patch adds a new DEBUG_ZBOOT option to allow the users to enable it to debug the compressed kernel support for a new board and this optoin should be disabled to reduce the kernel image size and speed up the kernel booting procedure when the compressed kernel support is stable. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> To: Ralf Baechle <ralf@linux-mips.org> Cc: Manuel Lauss <manuel.lauss@googlemail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/918/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove #if 0 r4k_update_mmu_cache_hwbugDavid Daney2010-02-27
| | | | | | | | | | The function is #if 0ed out. There are no other occurrences of its name in the tree. It is safe to remove. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/936/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: TXx9: Remove forced serial console settingYoichi Yuasa2010-02-27
| | | | | | | | | | It is not always used, even if it is available. Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/933/ Acked-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: AR7: Make ar7_register_devices much more durableAlexander Clouter2010-02-27
| | | | | | | | | | [Ralf: Fixed up the rejects and changed all the new printk(KERN_...); to pr_xxx() as suggested by Wu.] Signed-off-by: Alexander Clouter <alex@digriz.org.uk> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/920/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: AR7: Fix USB slave mem range typoAlexander Clouter2010-02-27
| | | | | | | Signed-off-by: Alexander Clouter <alex@digriz.org.uk> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/919/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: AR7: Whitespace hackingAlexander Clouter2010-02-27
| | | | | | | | | [Ralf: Fixed up reject and Wu's complaints about comment style.] Signed-off-by: Alexander Clouter <alex@digriz.org.uk> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/921/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Use strlcat() for the command line argumentsYoichi Yuasa2010-02-27
| | | | | | | Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/928/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Remove prom_getcmdline()Yoichi Yuasa2010-02-27
| | | | | | | Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/927/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Remove forced command line settingYoichi Yuasa2010-02-27
| | | | | | | | | It is not always used, even if it is available. Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/893/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Set __elf_platform for Octeon.David Daney2010-02-27
| | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/892/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Allow the auxv's elf_platform entry to be set.David Daney2010-02-27
| | | | | | | | | | | | | | | The userspace runtime linker uses the elf_platform to find the libraries optimized for the current CPU archecture variant. First we need to allow it to be set to something other than NULL. Follow-on patches will set some values for specific CPUs. GLIBC already does the right thing. The kernel just needs to supply good data. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/891/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MMC: AU1xMMC: Allow platforms to disable host capabilitiesManuel Lauss2010-02-27
| | | | | | | | | | | | | | Although the hardware supports a 4/8bit SD interface and the driver unconditionally advertises all hardware caps to the MMC core, not all datalines may actually be wired up. This patch introduces another field to au1xmmc platform data allowing platforms to disable certain advanced host controller features. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> To: linux-mmc@vger.kernel.org CC: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/460/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Deal with larger physical offsetsFlorian Fainelli2010-02-27
| | | | | | | | | | | | | | | | | AR7 has a larger physical offset than other MIPS based systems and therefore needs to setup its handlers beyond the usual KSEG0 range. When running the kernel in mapped mode this modification is also required. Remove function comment which is now incorrect. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Eugene Konev <ejka@imfi.kspu.ru> Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org To: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/889/ Patchwork: http://patchwork.linux-mips.org/patch/932/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Annotate set_except_vector with __initFlorian Fainelli2010-02-27
| | | | | | | | | | | All call sites of set_except_vector are already annotated with __init, so annotate that one too. Signed-off-by: Regards, Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org To: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/888/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Move arch/mips/mm/uasm.h to arch/mips/include/asm/uasm.hFlorian Fainelli2010-02-27
| | | | | | | | Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org To: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/887/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: PNX8550: Remove unnecessary export prom_getcmdline()Yoichi Yuasa2010-02-27
| | | | | | | Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/886/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: PNX833x: Remove unused prom_getcmdline()Yoichi Yuasa2010-02-27
| | | | | | | Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/885/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Support 36-bit iomem on 32-bit Au1x00pascal@pabr.org2010-02-27
| | | | | | | | | | | | I believe these changes are needed on Alchemy SoCs in order to use iomem above 4G with the usual platform_device machinery: - Set CONFIG_ARCH_PHYS_ADDR_T_64BIT to make resource_size_t 64-bit. - Increase IOMEM_RESOURCE_END so that platforms can register resources. To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/814/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson: Cleanup the halt and poweroff actionWu Zhangjin2010-02-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In the old source code, I have let halt and poweroff do the same action, but in reality, they have different meanings. As the manpage of shutdown shows: -r Reboot after shutdown. -H Halt action is to halt or drop into boot monitor on systems that support it. -P Halt action is to turn off the power. and in the real world, some machines(e.g. NAS) did not provide a power button and the shutdown works as reset, so, we need to provide a mechanism to let the users turn off the power safely without breaking the system, such a mechanism is "halt", which only put the system into a dead loop or a power-save mode and print some information to the screen to tell the users to turn off the power safely. $ shutdown -hH now /* loongson_halt, not turn off the power */ $ shutdown -hP now /* loongson_poweroff, work as poweroff */ Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Tested-by: Liu Shiwei <liushiwei@gmail.com> Cc: Liu Shiwei <liushiwei@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/883/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Simplify the weak annotation with __weakWu Zhangjin2010-02-27
| | | | | | | | | | | | | Found by $ find arch/mips/ -name "*.c" | xargs -i grep -H weak {} | grep -v __weak [Ralf: Made this bulletproof by including <linux/compiler.h>] Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/874/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: debug output for compressed kernelsManuel Lauss2010-02-27
| | | | | | | | | | | Hook up the compressed debug output for all Alchemy systems supported by current kernel codebase. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: Wu Zhangjin <wuzhangjin@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/879/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: AR7: Implement clock APIFlorian Fainelli2010-02-27
| | | | | | | | | | | | | | This patch makes the ar7 clock code implement the Linux clk API. Drivers using the various clocks available in the SoC are updated accordingly. Signed-off-by: Florian Fainelli <florian@openwrt.org> Acked-by: Wim Van Sebroeck <wim@iguana.be> To: linux-mips@linux-mips.org Cc: Wim Van Sebroeck <wim@iguana.be> Cc: netdev@vger.kernel.org Cc: David Miller <davem@davemloft.net> Patchwork: http://patchwork.linux-mips.org/patch/881/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: AR7: Implement gpiolibFlorian Fainelli2010-02-27
| | | | | | | | | This patch implements gpiolib for the AR7 SoC. Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/816/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: msp71xx: remove unused prom_getcmdline()Yoichi Yuasa2010-02-27
| | | | | | | Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/868/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Cleanup the Makefile of compressed kernel supportWu Zhangjin2010-02-27
| | | | | | | | | | This patch removes a useless "\" (line break) and tunes the format of a long line. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/869/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: AR7: replace prom_getcmdline() to arcs_cmdline[]Yoichi Yuasa2010-02-27
| | | | | | | Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/872/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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