aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/txx9/rbtx4927/irq.c
Commit message (Collapse)AuthorAge
* MIPS: TXx9: Microoptimize interrupt handlersAtsushi Nemoto2008-10-11
| | | | | | | | The IOC interrupt status register on RBTX49XX only have 8 bits. Use 8-bit version of __fls() to optimize interrupt handlers. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: RBTX4927: More explicit initializationAtsushi Nemoto2008-10-11
| | | | | | | | * Make sure all interrupts cleared on startup * Initialize some GPIOs Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] TXx9: Random cleanupAtsushi Nemoto2008-07-30
| | | | | | | | | | | | | | | | * Random cleanups spotted by checkpatch script. * Do not initialize panic_timeout. "panic=" kernel parameter can be used. * Do not add "ip=any" or "ip=bootp". This options is not board specific. * Do not add "root=/dev/nfs". This is default on CONFIG_ROOT_NFS. * Kill unused error checking. * Fix IRQ comment to match current code. * Kill some unneeded includes * ST0_ERL is already cleared in generic code. * conswitchp is initialized generic code. * __init is not needed in prototype. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] TXx9: Add 64-bit supportAtsushi Nemoto2008-07-20
| | | | | | | | | SYS_SUPPORTS_64BIT_KERNEL is enabled for RBTX4927/RBTX4938, but actually it was broken for long time (or from the beginning). Now it should work. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] TXx9: Make single kernel can support multiple boardsAtsushi Nemoto2008-07-15
| | | | | | | | Make single kernel can be used on RBTX4927/37/38. Also make some SoC-specific code independent from board-specific code. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] TXx9: Reorganize PCI codeAtsushi Nemoto2008-07-15
| | | | | | | | | | | | Split out PCIC dependent code and SoC dependent code from board dependent code. Now TX4927 PCIC code is independent from TX4927/TX4938 SoC code. Also fix some build problems on CONFIG_PCI=n. As a bonus, "FPCIB0 Backplane Support" is available for all TX39/TX49 boards and PCI66 support is available for all TX49 boards. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] TXx9: Reorganize codeAtsushi Nemoto2008-07-15
Move arch/mips/{jmr3927,tx4927,tx4938} into arch/mips/txx9/ tree. This will help more code sharing and maintainance. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>