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* [MIPS] Sibyte: Replace use of removed IO_SPACE_BASE with IOADDR.Ralf Baechle2007-11-15
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] BCM1480: Remove duplicate acknowledge of timer interrupt.Ralf Baechle2007-11-15
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Remove blank line.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Build fixes / dead code removal.Ralf Baechle2007-11-02
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Delete {sb1250,bcm1480}_steal_irq().Ralf Baechle2007-10-29
| | | | | | | | | They break the timer interrupt initialization and only seem to be a kludge for initialization happening in the wrong order. Further testing done by Thiemo confirms the suspicion that the other invocations also seem to have useless. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] time: SMP-proofing of Sibyte clockevent/clocksource code.Ralf Baechle2007-10-22
| | | | | | | | | | | The BCM148 has 4 cores but there are also just 4 generic timers available so use the ZBbus cycle counter instead of it. In addition the ZBbus counter also offers a much higher resolution and 64-bit counting so I'm considering a later complete conversion to it once I figure out if all members of the Sibyte SOC family support it - the docs seem to agree but the headers files seem to disagree ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] checkfiles: Fix "need space after that ','" errors.Ralf Baechle2007-10-11
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Implement clockevents for R4000-style cp0 count/compare interruptRalf Baechle2007-10-11
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] BCM1480: Fix computation of interrupt mask address register.Ralf Baechle2007-09-10
| | | | | | | | | | | | CC arch/mips/sibyte/bcm1480/irq.o arch/mips/sibyte/bcm1480/irq.c: In function 'bcm1480_mask_irq': arch/mips/sibyte/bcm1480/irq.c:112: warning: cast to pointer from integer of different size arch/mips/sibyte/bcm1480/irq.c:114: warning: cast to pointer from integer of different size arch/mips/sibyte/bcm1480/irq.c: In function 'bcm1480_unmask_irq': arch/mips/sibyte/bcm1480/irq.c:130: warning: cast to pointer from integer of different size arch/mips/sibyte/bcm1480/irq.c:132: warning: cast to pointer from integer of different size Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: CONFIG_SIBYTE_SB1250_DUART -> CONFIG_SERIAL_SB1250_DUARTRalf Baechle2007-08-26
| | | | | | | | This is needed since the Sibyte serial driver was exchanged. Issue report by Imre Kaloz <kaloz@openwrt.org>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] BCM1480: Fix setting of irq affinity.Mark Mason2007-03-29
| | | | | Signed-off-by: Mark Mason <mason@broadcom.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix and cleanup the mess that a dozen prom_printf variants are.Ralf Baechle2007-03-04
| | | | | | early_printk is a so much saner thing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] use name instead of typename for each irq_chipAtsushi Nemoto2007-02-06
| | | | | | | The "typename" field was obsoleted by the "name" field. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IRQ cleanupsAtsushi Nemoto2006-11-29
| | | | | | | | | | | | | | | | | | | | | This is a big irq cleanup patch. * Use set_irq_chip() to register irq_chip. * Initialize .mask, .unmask, .mask_ack field. Functions for these method are already exist in most case. * Do not initialize .startup, .shutdown, .enable, .disable fields if default routines provided by irq_chip_set_defaults() were suitable. * Remove redundant irq_desc initializations. * Remove unnecessary local_irq_save/local_irq_restore, spin_lock. With this cleanup, it would be easy to switch to slightly lightwait irq flow handlers (handle_level_irq(), etc.) instead of __do_IRQ(). Though whole this patch is quite large, changes in each irq_chip are not quite simple. Please review and test on your platform. Thanks. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Cleanup unnecessary <asm/ptrace.h> inclusions.Ralf Baechle2006-10-08
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Complete fixes after removal of pt_regs argument to int handlers.Ralf Baechle2006-10-07
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] BCM1480: Mask pending interrupts against c0_status.im.Ralf Baechle2006-10-03
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix 32-bit kernel by replacing 64-bit-only code.Ralf Baechle2006-09-27
| | | | | | | dclz() expects its 64-bit argument being passed as a single register but on 32-bit kernels it'll actually be in a register pair. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] BCM1480: Fix fatal typo in the rewritten interrupt handler.Thiemo Seufer2006-07-13
| | | | | Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Improve interrupt latency again for sb1250/bcm1480Thiemo Seufer2006-07-13
| | | | | | | | | this patch restores the behaviour of the old (assembly-written) interrupt handler, the handler is left as soon as a single interrupt cause is handled. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Eleminate interrupt migration helper use.Ralf Baechle2006-07-13
| | | | | | | | | > #define hw_interrupt_type irq_chip > typedef struct irq_chip hw_irq_controller; > #define no_irq_type no_irq_chip > typedef struct irq_desc irq_desc_t; Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Remove obsolete #include <linux/config.h>Jörn Engel2006-06-30
| | | | | Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
* [PATCH] genirq: rename desc->handler to desc->chipIngo Molnar2006-06-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch-queue improves the generic IRQ layer to be truly generic, by adding various abstractions and features to it, without impacting existing functionality. While the queue can be best described as "fix and improve everything in the generic IRQ layer that we could think of", and thus it consists of many smaller features and lots of cleanups, the one feature that stands out most is the new 'irq chip' abstraction. The irq-chip abstraction is about describing and coding and IRQ controller driver by mapping its raw hardware capabilities [and quirks, if needed] in a straightforward way, without having to think about "IRQ flow" (level/edge/etc.) type of details. This stands in contrast with the current 'irq-type' model of genirq architectures, which 'mixes' raw hardware capabilities with 'flow' details. The patchset supports both types of irq controller designs at once, and converts i386 and x86_64 to the new irq-chip design. As a bonus side-effect of the irq-chip approach, chained interrupt controllers (master/slave PIC constructs, etc.) are now supported by design as well. The end result of this patchset intends to be simpler architecture-level code and more consolidation between architectures. We reused many bits of code and many concepts from Russell King's ARM IRQ layer, the merging of which was one of the motivations for this patchset. This patch: rename desc->handler to desc->chip. Originally i did not want to do this, because it's a big patch. But having both "desc->handler", "desc->handle_irq" and "action->handler" caused a large degree of confusion and made the code appear alot less clean than it truly is. I have also attempted a dual approach as well by introducing a desc->chip alias - but that just wasnt robust enough and broke frequently. So lets get over with this quickly. The conversion was done automatically via scripts and converts all the code in the kernel. This renaming patch is the first one amongst the patches, so that the remaining patches can stay flexible and can be merged and split up without having some big monolithic patch act as a merge barrier. [akpm@osdl.org: build fix] [akpm@osdl.org: another build fix] Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [MIPS] Rewrite all the assembler interrupt handlers to C.Ralf Baechle2006-04-18
| | | | | | | | | | | | Saves like 1,600 lines of code, is way easier to debug, compilers frequently do a better job than the cut and paste type of handlers many boards had. And finally having all the stuff done in a single place also means alot of bug potencial for the MT ASE is gone. The only surviving handler in assembler is the DECstation one; I hope Maciej will rewrite it. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix compiler warnings in arch/mips/sibyte/bcm1480/irq.cMartin Michlmayr2006-02-21
| | | | | | | | | | | | | Fix the following compiler warnings: CC arch/mips/sibyte/bcm1480/irq.o arch/mips/sibyte/bcm1480/irq.c: In function ‘bcm1480_set_affinity’: arch/mips/sibyte/bcm1480/irq.c:168: warning: ISO C90 forbids mixed declarations and code arch/mips/sibyte/bcm1480/irq.c: In function ‘ack_bcm1480_irq’: arch/mips/sibyte/bcm1480/irq.c:230: warning: ISO C90 forbids mixed declarations and code Signed-off-by: Martin Michlmayr <tbm@cyrius.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Add support for BCM1480 family of chips.Andrew Isaacson2005-10-29
- Kconfig and Makefile changes - arch/mips/sibyte/bcm1480/ - changes to sibyte common code to support 1480 Signed-Off-By: Andy Isaacson <adi@broadcom.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>