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* MIPS: VR5500: Enable prefetchShinya Kuribayashi2009-03-23
| | | | | Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix oops in dma_unmap_page on not coherent mips platformsJan Nikitenko2009-03-23
| | | | | | | | | | | dma_cache_wback_inv() expects virtual address, but physical was provided due to translation via plat_dma_addr_to_phys(). If replaced with dma_addr_to_virt(), page fault oops from dma_unmap_page() is gone on au1550 platform. Signed-off-by: Jan Nikitenko <jan.nikitenko@gmail.com> Acked-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: NEC VR5500 processor support fixupShinya Kuribayashi2009-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | Current VR5500 processor support lacks of some functions which are expected to be configured/synthesized on arch initialization. Here're some VR5500A spec notes: * All execution hazards are handled in hardware. * Once VR5500A stops the operation of the pipeline by WAIT instruction, it could return from the standby mode only when either a reset, NMI request, or all enabled interrupts is/are detected. In other words, if interrupts are disabled by Status.IE=0, it keeps in standby mode even when interrupts are internally asserted. Notes on WAIT: The operation of the processor is undefined if WAIT insn is in the branch delay slot. The operation is also undefined if WAIT insn is executed when Status.EXL and Status.ERL are set to 1. * VR5500A core only implements the Load prefetch. With these changes, it boots fine. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: CVE-2009-0029: Enable syscall wrappers.Ralf Baechle2009-02-27
| | | | | | | Thanks to David Daney helping with debugging and testing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: David Daney <ddaney@caviumnetworks.com>
* MIPS: Port "mm: invoke oom-killer from page fault" from UML / x86Ralf Baechle2009-01-30
| | | | | | Original commit 1c0fe6e3bda0464728c23c8d84aa47567e8b716c. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Avoid destructive invalidation on partial cachelines.Ralf Baechle2009-01-30
| | | | | | See discussion e9c3a7c20901051031y528d0d31r18d44c5096c59e0@mail.gmail.com. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Only write c0_framemask on CPUs which have this register.Ralf Baechle2009-01-11
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Adjust the dma-common.c platform hooks.David Daney2009-01-11
| | | | | | | | | We add a dev parameter to plat_unmap_dma_mem(), and hooks for plat_dma_supported() and plat_extra_sync_for_device() which should be nop changes for all existing targets. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add Cavium OCTEON slot into proper tlb category.David Daney2009-01-11
| | | | | | | | | | Expand the case statement for build_tlb_write_entry so that it does the right thing on Cavium CPU variants. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Hook up Cavium OCTEON in arch/mips.David Daney2009-01-11
| | | | | | | | | | Take all the OCTEON specific files that were added, and hook them into the build system for the arch/mips. For versions of GCC that lack OCTEON support, override gas target architecture. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Hook Cavium OCTEON cache init into cache.cDavid Daney2009-01-11
| | | | | | | | | Follow precedent of other boards, and hook-up the CPU specific cache init. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.David Daney2009-01-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are the rest of the new files needed to add OCTEON processor support to the Linux kernel. Other than Makefile and Kconfig which should be obvious, we have: csrc-octeon.c -- Clock source driver for OCTEON. dma-octeon.c -- Helper functions for mapping DMA memory. flash_setup.c -- Register on-board flash with the MTD subsystem. octeon-irq.c -- OCTEON interrupt controller managment. octeon-memcpy.S -- Optimized memcpy() implementation. serial.c -- Register 8250 platform driver and early console. setup.c -- Early architecture initialization. smp.c -- OCTEON SMP support. octeon_switch.S -- Scheduler context switch for OCTEON. c-octeon.c -- OCTEON cache controller support. cex-oct.S -- OCTEON cache exception handler. asm/mach-cavium-octeon/*.h -- Architecture include files. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/cavium-octeon/Kconfig create mode 100644 arch/mips/cavium-octeon/Makefile create mode 100644 arch/mips/cavium-octeon/csrc-octeon.c create mode 100644 arch/mips/cavium-octeon/dma-octeon.c create mode 100644 arch/mips/cavium-octeon/flash_setup.c create mode 100644 arch/mips/cavium-octeon/octeon-irq.c create mode 100644 arch/mips/cavium-octeon/octeon-memcpy.S create mode 100644 arch/mips/cavium-octeon/serial.c create mode 100644 arch/mips/cavium-octeon/setup.c create mode 100644 arch/mips/cavium-octeon/smp.c create mode 100644 arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/irq.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/war.h create mode 100644 arch/mips/include/asm/octeon/octeon.h create mode 100644 arch/mips/kernel/octeon_switch.S create mode 100644 arch/mips/mm/c-octeon.c create mode 100644 arch/mips/mm/cex-oct.S
* MIPS: Add missing calls to plat_unmap_dma_mem.David Daney2008-12-12
| | | | | | | | dma_free_noncoherent() and dma_free_coherent() are missing calls to plat_unmap_dma_mem(). This patch adds them. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: IP22: Make indy_sc_ops variable staticDmitri Vorobiev2008-11-20
| | | | | | | | | The indy_sc_ops variable in arch/mips/mm/sc-ip22.c is needlessly defined global, and this patch makes it static. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.fi> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
* MIPS: Add CONFIG_CPU_R5500 for NEC VR5500 series processorsShinya Kuribayashi2008-10-27
| | | | | | | | | | | | We already have sufficient infrastructure to support VR5500 and VR5500A series processors. Here's a Makefile support to make it selectable by ports, and enable it for NEC EMMA2RH Markeins board. This patch also fixes a confused target help, and adds 1Gb PageMask bits supported by VR5500 and its variants. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Don't unmap the memory for dma_sync*.David Daney2008-10-27
| | | | | | | | | We were getting away with this for so long only because the only platform with a non-empty plat_unmap_dma_mem() doesn't call dma_sync_sg_for_cpu() and dma_sync_sg_for_device() from its commonly used drivers. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] TX39xx: Add missing local_flush_icache_range initializationAtsushi Nemoto2008-09-05
| | | | | | | | | Commmit 59e39ecd933ba49eb6efe84cbfa5597a6c9ef18a ("Fix WARNING: at kernel/smp.c:290") introduced local_flush_icache_range but lacks initialization for some TX39 case. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix WARNING: at kernel/smp.c:290Thomas Bogendoerfer2008-09-05
| | | | | | | | | | | trap_init issues flush_icache_range(), which uses ipi functions to get icache flushing done on all cpus. But this is done before interrupts are enabled and caused WARN_ON messages. This changeset introduces a new local_flush_icache_range() and uses it before interrupts (and additional CPUs) are enabled to avoid this problem. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] tlb-r4k: Nuke broken paranoia error test.Ralf Baechle2008-07-30
| | | | | | | | | Bug originally found and reported by Julia Lawall <julia@diku.dk>. I decieded that the whole error check was mostly useless paranoia and should be discarded. It would only ever trigger if r3k_have_wired_reg has a wrong value. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* mips: use generic show_mem()Johannes Weiner2008-07-26
| | | | | | | | | | | | | | | | | | | Remove arch-specific show_mem() in favor of the generic version. This also removes the following redundant information display: - pages in swapcache, printed by show_swap_cache_info() where show_mem() calls show_free_areas(), which calls show_swap_cache_info(). And show_mem() does now actually print something on configurations with multiple nodes. Signed-off-by: Johannes Weiner <hannes@saeurebad.de> Acked-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* dma-mapping: add the device argument to dma_mapping_error()FUJITA Tomonori2008-07-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add per-device dma_mapping_ops support for CONFIG_X86_64 as POWER architecture does: This enables us to cleanly fix the Calgary IOMMU issue that some devices are not behind the IOMMU (http://lkml.org/lkml/2008/5/8/423). I think that per-device dma_mapping_ops support would be also helpful for KVM people to support PCI passthrough but Andi thinks that this makes it difficult to support the PCI passthrough (see the above thread). So I CC'ed this to KVM camp. Comments are appreciated. A pointer to dma_mapping_ops to struct dev_archdata is added. If the pointer is non NULL, DMA operations in asm/dma-mapping.h use it. If it's NULL, the system-wide dma_ops pointer is used as before. If it's useful for KVM people, I plan to implement a mechanism to register a hook called when a new pci (or dma capable) device is created (it works with hot plugging). It enables IOMMUs to set up an appropriate dma_mapping_ops per device. The major obstacle is that dma_mapping_error doesn't take a pointer to the device unlike other DMA operations. So x86 can't have dma_mapping_ops per device. Note all the POWER IOMMUs use the same dma_mapping_error function so this is not a problem for POWER but x86 IOMMUs use different dma_mapping_error functions. The first patch adds the device argument to dma_mapping_error. The patch is trivial but large since it touches lots of drivers and dma-mapping.h in all the architecture. This patch: dma_mapping_error() doesn't take a pointer to the device unlike other DMA operations. So we can't have dma_mapping_ops per device. Note that POWER already has dma_mapping_ops per device but all the POWER IOMMUs use the same dma_mapping_error function. x86 IOMMUs use device argument. [akpm@linux-foundation.org: fix sge] [akpm@linux-foundation.org: fix svc_rdma] [akpm@linux-foundation.org: build fix] [akpm@linux-foundation.org: fix bnx2x] [akpm@linux-foundation.org: fix s2io] [akpm@linux-foundation.org: fix pasemi_mac] [akpm@linux-foundation.org: fix sdhci] [akpm@linux-foundation.org: build fix] [akpm@linux-foundation.org: fix sparc] [akpm@linux-foundation.org: fix ibmvscsi] Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Cc: Muli Ben-Yehuda <muli@il.ibm.com> Cc: Andi Kleen <andi@firstfloor.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@elte.hu> Cc: Avi Kivity <avi@qumranet.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2008-07-15
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (54 commits) [MIPS] Remove mips_machtype for LASAT machines [MIPS] Remove mips_machtype from EMMA2RH machines [MIPS] Remove mips_machtype from ARC based machines [MIPS] MTX-1 flash partition setup move to platform devices registration [MIPS] TXx9: cleanup and fix some sparse warnings [MIPS] TXx9: rename asm-mips/mach-jmr3927 to asm-mips/mach-tx39xx [MIPS] remove machtype for group Toshiba [MIPS] separate rbtx4927_time_init() and rbtx4937_time_init() [MIPS] separate rbtx4927_arch_init() and rbtx4937_arch_init() [MIPS] txx9_cpu_clock setup move to rbtx4927_time_init() [MIPS] txx9_board_vec set directly without mips_machtype [MIPS] IP22: Add platform device for Indy volume buttons [MIPS] cmbvr4133: Remove support [MIPS] remove wrppmc_machine_power_off() [MIPS] replace inline assembler to cpu_wait() [MIPS] IP22/28: Add platform devices for HAL2 [MIPS] TXx9: Update and merge defconfigs [MIPS] TXx9: Make single kernel can support multiple boards [MIPS] TXx9: Update defconfigs [MIPS] TXx9: Reorganize PCI code ...
| * [MIPS] Make two functions staticDmitri Vorobiev2008-07-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following routines uasm_rel_highest() uasm_rel_higher() are needlessly defined global. This patch makes them static. Compile-tested using a customized config for the Malta board. Booting the same board up to the shell prompt was also successful with this patch applied. Spotted by sparse. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@movial.fi> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | Merge branch 'generic-ipi' into generic-ipi-for-linusIngo Molnar2008-07-15
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/powerpc/Kconfig arch/s390/kernel/time.c arch/x86/kernel/apic_32.c arch/x86/kernel/cpu/perfctr-watchdog.c arch/x86/kernel/i8259_64.c arch/x86/kernel/ldt.c arch/x86/kernel/nmi_64.c arch/x86/kernel/smpboot.c arch/x86/xen/smp.c include/asm-x86/hw_irq_32.h include/asm-x86/hw_irq_64.h include/asm-x86/mach-default/irq_vectors.h include/asm-x86/mach-voyager/irq_vectors.h include/asm-x86/smp.h kernel/Makefile Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * smp_call_function: get rid of the unused nonatomic/retry argumentJens Axboe2008-06-26
| | | | | | | | | | | | | | | | It's never used and the comments refer to nonatomic and retry interchangably. So get rid of it. Acked-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
* | [MIPS] Fix 32bit kernels on R4k with 128 byte cache line sizeThomas Bogendoerfer2008-07-08
| | | | | | | | | | | | | | | | | | | | | | | | The generated copy_page for R4k CPU with a 128 byte cache line size used Create Dirty Exclusive cache line operations even if only part of the cache line was filled. This change avoids generating cache operations, if only part of the cache line size is copied in one loop. It also increases the maxmimum loop size, because the generated code even fits into the available space for r4k CPUs with 128 byte cache line size. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | [MIPS] Atlas, decstation: Fix section mismatches triggered by defconfigsShane McDonald2008-07-08
|/ | | | | | | | Resolve these mismatches by defining affected functions with the __cpuinit attribute, rather than __init. Signed-off-by: Shane McDonald <mcdonald.shane@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix buggy use of kmap_coherent.Ralf Baechle2008-06-16
| | | | | | | | Assuming the call of kmap_coherent in local_r4k_flush_cache_page doesn't need fixing this was skipped in fcae549295bcae801ac48fc1c2030ab8cc487020. Turns out it needed the same change after all. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix the fix for divide by zero error in build_{clear,copy}_pageAtsushi Nemoto2008-06-16
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix build for PNX platforms.Ralf Baechle2008-06-16
| | | | | | Build error was caused by commit 351336929ccf222ae38ff0cb7a8dd5fd5c6236a0. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Export empty_zero_page for sake of the ext4 module.Ralf Baechle2008-06-16
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Fix divide by zero error in build_clear_page() and build_copy_page()Yoichi Yuasa2008-06-05
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] R4700: Fix build_tlb_probe_entryThomas Bogendoerfer2008-06-05
| | | | | | | | Treat R4700 like R4600 in build_tlb_probe_entry. Without this fix kernel will lock up. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] unexport __kmap_atomic_to_pageAdrian Bunk2008-05-12
| | | | | | | This patch removes the no longer used export of __kmap_atomic_to_page. Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] unexport copy_from_user_page()Dmitri Vorobiev2008-04-28
| | | | | | | | | No users for the copy_from_user_page() routine exist outside of the core kernel code. Therefore, EXPORT_SYMBOL(copy_from_user_page) is useless, and this patch removes it. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] unexport copy_to_user_page()Dmitri Vorobiev2008-04-28
| | | | | | | | | The copy_to_user_page() function is called only in the core kernel code. Therefore, there is no need to export it. This patch removes EXPORT_SYMBOL(copy_to_user_page). Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] unexport copy_user_highpage()Dmitri Vorobiev2008-04-28
| | | | | | | | | The copy_user_highpage() routine has no users outside of the core kernel code, so exporting this symbol is pointless. This patch removes EXPORT_SYMBOL(copy_user_highpage). Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] remove redundant display of free swap space in show_mem()Johannes Weiner2008-04-28
| | | | | | Signed-off-by: Johannes Weiner <hannes@saeurebad.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add support for MIPS CMP platform.Ralf Baechle2008-04-28
| | | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Allow setting of the cache attribute at run time.Chris Dearman2008-04-28
| | | | | | | | Slightly tacky, but there is a precedent in the sparc archirecture code. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] All MIPS32 processors support64-bit physical addresses.Chris Dearman2008-04-28
| | | | | | | Still, only the 4K may actually implement it. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Reimplement clear_page/copy_pageThiemo Seufer2008-04-28
| | | | | | | | | | | | | | | | | Fold the SB-1 specific implementation of clear_page/copy_page in the generic version, and rewrite that one in tlbex style. The immediate benefits: - It converts the compile-time workaround for SB-1 pass 1 prefetches to a more efficient run-time check. - It allows adjustment of loop unfolling, which helps to reduce the number of redundant cdex cache ops. - It fixes some esoteric cornercases (the cache line length calculations can go wrong, and support for 64k pages without prefetch instructions will overflow the addiu immediate). - Somewhat better guesses of "good" prefetch values. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Handle aliases in vmalloc correctly.Ralf Baechle2008-04-07
| | | | | | | flush_cache_vmap / flush_cache_vunmap were calling flush_cache_all which - having been deprecated - turned into a nop ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add missing 4KEC TLB refill handlerThomas Bogendoerfer2008-04-01
| | | | | | | | Early 4KEc were MIPS32r1 and therefore need some love to get a TLB refill handler. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix loads of section missmatchesRalf Baechle2008-03-12
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix typo in commentThiemo Seufer2008-03-12
| | | | | | | We support now other page sizes as well. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SB1: Fix CONFIG_SIBYTE_DMA_PAGEOPS build failure.Thiemo Seufer2008-02-19
| | | | | | | | | Fix type mismatch warnings for 64-bit kernel builds which trigger -Werror. The problem affects only SB-1 kernels with CONFIG_SIBYTE_DMA_PAGEOPS enabled. Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix buggy invocations of kmap_coherent()Ralf Baechle2008-02-19
| | | | | | | | kmap_coherent will only work correctly if the page it is called on is not marked dirty. If it's dirty the kernel address of the page should be used instead of a temporary mapping. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Handle I-cache coherency in flush_cache_range()Ralf Baechle2008-02-19
| | | | | | | | | | | | | | | | | | | | | | So far flush_cache_range() did't consider the I-cache largely because it did rarely ever matter to real world code. This was working primarily because normally code and data are don't share the same pages - with the exception of MIPS16 code which uses address constants embedded between the code. The following sequence of events may break the code: o MIPS16 executable being loaded o dynamic linker relocates the address constants embedded into the code: o Uses mprotect(2) to make code pages PROT_READ|PROT_WRITE o Performs the actual relocations by writing to the pages which likely are COW. Because no PROT_EXEC is set I-cache coherence will not be considered. o Uses mprotect(2) to switch code pages back to PROT_READ|PROT_EXEC. This results in a call to flush_cache_range() which also does not consider I-caches. o => executing the page just having been relocated may now result in the I-cache getting refilled with stale data from memory. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* arch/mips/: Spelling fixesJoe Perches2008-02-03
| | | | | Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Adrian Bunk <bunk@kernel.org>
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