aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/mm
Commit message (Expand)AuthorAge
* Fix wrong comment.Ralf Baechle2005-10-29
* Fixup a few lose ends in explicit support for MIPS R1/R2.Ralf Baechle2005-10-29
* Don't copy SB1 cache error handler to uncached memory.Ralf Baechle2005-10-29
* Fix stale comment in c-sb1.c.Andrew Isaacson2005-10-29
* Cleanup the mess in cpu_cache_init.Ralf Baechle2005-10-29
* Use R4000 TLB routines for SB1 also.Ralf Baechle2005-10-29
* Sync c-tx39.c with c-r4k.c.Atsushi Nemoto2005-10-29
* Add/Fix missing bit of R4600 hit cacheop workaround.Thiemo Seufer2005-10-29
* Minor code cleanup.Thiemo Seufer2005-10-29
* R4600 v2.0 needs a nop before tlbp.Thiemo Seufer2005-10-29
* Don't set up a sg dma address if we have no page address for some reason.Thiemo Seufer2005-10-29
* More .set push/pop.Thiemo Seufer2005-10-29
* Let r4600 PRID detection match only legacy CPUs, cleanups.Thiemo Seufer2005-10-29
* Handle mtc0 - tlb write hazard for VR5432.Ralf Baechle2005-10-29
* Avoid SMP cacheflushes. This is a minor optimization of startup butRalf Baechle2005-10-29
* Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it.Pete Popov2005-10-29
* More AP / SP bits for the 34K, the Malta bits and things. Still wantsRalf Baechle2005-10-29
* Mark a few variables __read_mostly.Ralf Baechle2005-10-29
* MIPS R2 instruction hazard handling.Ralf Baechle2005-10-29
* Detect the 34K.Ralf Baechle2005-10-29
* Define kmap_atomic_pfn() for MIPS.Ralf Baechle2005-10-29
* Date: Fri Jul 8 20:10:17 2005 +0000Ralf Baechle2005-10-29
* Rename CONFIG_CPU_MIPS{32,64} to CONFIG_CPU_MIPS{32|64}_R1.Ralf Baechle2005-10-29
* Avoid tlbw* hazards for the R4600/R4700/R5000.Maciej W. Rozycki2005-10-29
* Inline ioremap() calls for constant addresses that map to KSEG1.Maciej W. Rozycki2005-10-29
* Fix the diagnostic dump for the XTLB refill handler.Maciej W. Rozycki2005-10-29
* Fix a diagnostic message.Maciej W. Rozycki2005-10-29
* Use macros for the RM7k cp0.config bits instead of magic numbers.Maciej W. Rozycki2005-10-29
* Optimize R3k TLB Load/Store/Modified handlers, by schedulingMaciej W. Rozycki2005-10-29
* Fill R3k load delay slots properly.Maciej W. Rozycki2005-10-29
* Only dump instructions actually emitted.Maciej W. Rozycki2005-10-29
* Handle _PAGE_DIRTY correctly for CONFIG_64BIT_PHYS_ADDR on 32bit CPUs.Thiemo Seufer2005-10-29
* Better interface to run uncached cache setup code.Thiemo Seufer2005-10-29
* Arrested for multiple offences of header file inclusion.Ralf Baechle2005-10-29
* Fix race conditions for read_c0_entryhi. Remove broken ASID masks inThiemo Seufer2005-10-29
* Remove useless casts. Fix formatting.Maciej W. Rozycki2005-10-29
* Fix 64bit SMP TLB handler and stack frame handling, optimize 32bit SMPThiemo Seufer2005-10-29
* R4300 delay slot.Ralf Baechle2005-10-29
* Reformat; cosmetic cleanups.Ralf Baechle2005-10-29
* Export shm_align_mask and flush_data_cache_page.Ralf Baechle2005-10-29
* Gcc 4.0 fixes.Ralf Baechle2005-10-29
* Sparseify MIPS.Ralf Baechle2005-10-29
* Base Au1200 2.6 support.Pete Popov2005-10-29
* Fix initialization. Unbreak the wait-for-completion loops. Code cleanup.Thiemo Seufer2005-10-29
* Switch SiByte drivers back to __raw_*() functions.Maciej W. Rozycki2005-10-29
* Handle addresses beyond VMALLOC_END correctly.Thiemo Seufer2005-10-29
* Use intermediate variable.Thiemo Seufer2005-10-29
* Moves a test which determines if we actually need to perform aRalf Baechle2005-10-29
* Update MIPS to use the 4-level pagetable code thereby getting rid ofRalf Baechle2005-10-29
* 25Kf is also physically indexed.Ralf Baechle2005-10-29
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 22:49:52 -0500