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Commit message (Expand)AuthorAge
* [MIPS] Fix vectored interrupt support in TLB exception handler generator.Ralf Baechle2006-04-18
* [MIPS] Cleanup free_initmem the same way as i386 did.Ralf Baechle2006-04-18
* [PATCH] unify PFN_* macrosDave Hansen2006-03-27
* [PATCH] s/;;/;/gAlexey Dobriyan2006-03-24
* [PATCH] remove set_page_count() outside mm/Nick Piggin2006-03-22
* [PATCH] mm: split highorder pagesNick Piggin2006-03-22
* [MIPS] TX49XX has prefetch.Atsushi Nemoto2006-03-21
* [MIPS] Kill tlb-andes.c.Thiemo Seufer2006-03-21
* [MIPS] War on whitespace: cleanup initial spaces followed by tabs.Ralf Baechle2006-03-21
* [MIPS] Remove CONFIG_BUILD_ELF64.Ralf Baechle2006-03-21
* [MIPS] sc-rm7k.c cleanupAtsushi Nemoto2006-03-21
* [MIPS] local_r4k_flush_cache_page fixAtsushi Nemoto2006-03-18
* [MIPS] Scatter a bunch of __init over tlbex.c.Ralf Baechle2006-03-09
* [MIPS] Initialize S-cache function pointers even on S-cache-less CPUs.Ralf Baechle2006-02-28
* [MIPS] Sibyte: #if CONFIG_* doesn't fly.Ralf Baechle2006-02-21
* [MIPS] Add protected_blast_icache_range, blast_icache_range, etc.Atsushi Nemoto2006-02-14
* [MIPS] Support /proc/kcore for MIPSDaniel Jacobowitz2006-02-07
* [MIPS] Remove wrong __user tags.Atsushi Nemoto2006-02-07
* MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.Ralf Baechle2006-01-10
* [PATCH] mips: setup_zero_pages count 1Hugh Dickins2005-12-12
* [MIPS] Use reset_page_mapcount to initialize empty_zero_page usage counter.Ralf Baechle2005-12-01
* [PATCH] mm: init_mm without ptlockHugh Dickins2005-10-30
* SB1 cache exception handling.Andrew Isaacson2005-10-29
* Add support for SB1A CPU.Andrew Isaacson2005-10-29
* Fix zero length sys_cacheflushAtsushi Nemoto2005-10-29
* Rename page argument of flush_cache_page to something more descriptive.Ralf Baechle2005-10-29
* Fix wrong comment.Ralf Baechle2005-10-29
* Fixup a few lose ends in explicit support for MIPS R1/R2.Ralf Baechle2005-10-29
* Don't copy SB1 cache error handler to uncached memory.Ralf Baechle2005-10-29
* Fix stale comment in c-sb1.c.Andrew Isaacson2005-10-29
* Cleanup the mess in cpu_cache_init.Ralf Baechle2005-10-29
* Use R4000 TLB routines for SB1 also.Ralf Baechle2005-10-29
* Sync c-tx39.c with c-r4k.c.Atsushi Nemoto2005-10-29
* Add/Fix missing bit of R4600 hit cacheop workaround.Thiemo Seufer2005-10-29
* Minor code cleanup.Thiemo Seufer2005-10-29
* R4600 v2.0 needs a nop before tlbp.Thiemo Seufer2005-10-29
* Don't set up a sg dma address if we have no page address for some reason.Thiemo Seufer2005-10-29
* More .set push/pop.Thiemo Seufer2005-10-29
* Let r4600 PRID detection match only legacy CPUs, cleanups.Thiemo Seufer2005-10-29
* Handle mtc0 - tlb write hazard for VR5432.Ralf Baechle2005-10-29
* Avoid SMP cacheflushes. This is a minor optimization of startup butRalf Baechle2005-10-29
* Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it.Pete Popov2005-10-29
* More AP / SP bits for the 34K, the Malta bits and things. Still wantsRalf Baechle2005-10-29
* Mark a few variables __read_mostly.Ralf Baechle2005-10-29
* MIPS R2 instruction hazard handling.Ralf Baechle2005-10-29
* Detect the 34K.Ralf Baechle2005-10-29
* Define kmap_atomic_pfn() for MIPS.Ralf Baechle2005-10-29
* Date: Fri Jul 8 20:10:17 2005 +0000Ralf Baechle2005-10-29
* Rename CONFIG_CPU_MIPS{32,64} to CONFIG_CPU_MIPS{32|64}_R1.Ralf Baechle2005-10-29
* Avoid tlbw* hazards for the R4600/R4700/R5000.Maciej W. Rozycki2005-10-29
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