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* [MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2Fuxin Zhang2007-07-10
| | | | | Signed-off-by: Fuxin Zhang <zhangfx@lemote.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Avoid dupliate D-cache flush on R400C / R4400 SC and MC variants.Ralf Baechle2006-11-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Remove redundant r4k_blast_icache() callsAtsushi Nemoto2006-11-29
| | | | | | | | | | | | r4k_flush_cache_all() and r4k_flush_cache_mm() case: these are noop if the CPU did not have dc_aliases. It would mean we do not need to care about icache here. r4k_flush_cache_range case: if r4k_flush_cache_mm() did not need to care about icache, it would be same for this function. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Remove __flush_icache_pageAtsushi Nemoto2006-10-01
| | | | | | | __flash_icache_page is unused, so kill it. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] c-r4k: Convert init functions from inline to __init.Ralf Baechle2006-09-27
| | | | | | | | With more recent compilers inline doesn't necessarily means a function will always be inlined. So leave that decission to the compiler and make the function as __init. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Do not use drop_mmu_context to flusing other task's VIPT I-cache.Atsushi Nemoto2006-09-27
| | | | | | | | | | c-r4k.c and c-sb1.c use drop_mmu_context() to flush virtually tagged I-caches, but this does not work for flushing other task's icache. This is for example triggered by copy_to_user_page() called from ptrace(2). Use indexed flush for such cases. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Retire flush_icache_page from mm use.Ralf Baechle2006-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the 34K the redundant cache operations were causing excessive stalls resulting in realtime code running on the second VPE missing its deadline. For all other platforms this patch is just a significant performance improvment as illustrated by below benchmark numbers. Processor, Processes - times in microseconds - smaller is better ------------------------------------------------------------------------------ Host OS Mhz null null open slct sig sig fork exec sh call I/O stat clos TCP inst hndl proc proc proc --------- ------------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 25Kf 2.6.18-rc4 533 0.49 1.16 7.57 33.4 30.5 1.34 12.4 5497 17.K 54.K 25Kf 2.6.18-rc4-p 533 0.49 1.16 6.68 23.0 30.7 1.36 8.55 5030 16.K 48.K 4Kc 2.6.18-rc4 80 4.21 15.0 131. 289. 261. 16.5 258. 18.K 70.K 227K 4Kc 2.6.18-rc4-p 80 4.34 13.1 128. 285. 262. 18.2 258. 12.K 52.K 176K 34Kc 2.6.18-rc4 40 5.01 14.0 61.6 90.0 477. 17.9 94.7 29.K 108K 342K 34Kc 2.6.18-rc4-p 40 4.98 13.9 61.2 89.7 475. 17.6 93.7 8758 44.K 158K BCM1480 2.6.18-rc4 700 0.28 0.60 3.68 5.92 16.0 0.78 5.08 931. 3163 15.K BCM1480 2.6.18-rc4-p 700 0.28 0.61 3.65 5.85 16.0 0.79 5.20 395. 1464 8385 TX49-16K 2.6.18-rc3 197 0.73 2.41 19.0 37.8 82.9 2.94 17.5 4438 14.K 56.K TX49-16K 2.6.18-rc3-p 197 0.73 2.40 19.9 36.3 82.9 2.94 23.4 2577 9103 38.K TX49-32K 2.6.18-rc3 396 0.36 1.19 6.80 11.8 41.0 1.46 8.17 2738 8465 32.K TX49-32K 2.6.18-rc3-p 396 0.36 1.19 6.82 10.2 41.0 1.46 8.18 1330 4638 18.K Original patch by me with enhancements by Atsushi Nemoto. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
* [MIPS] c-r4k: Typo fix.Ralf Baechle2006-09-27
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] vr41xx: Replace magic number for P4K bit with symbol.Yoichi Yuasa2006-07-13
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] vr41xx: Changed workaround to recommended methodYoichi Yuasa2006-07-13
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] VR41xx: Set VR41_CONF_BP only for PrId 0x0c80.Yoichi Yuasa2006-07-13
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Use the proper technical term for naming some of the cache macros.Ralf Baechle2006-07-13
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Remove obsolete #include <linux/config.h>Jörn Engel2006-06-30
| | | | | Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
* [MIPS] 74K: Assume it will also have an AR bit in config7Ralf Baechle2006-06-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Treat CPUs with AR bit as physically indexed.Ralf Baechle2006-06-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix handling of 0 length I & D caches.Chris Dearman2006-06-29
| | | | | | | Don't ask. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] MIPS32/MIPS64 secondary cache managementChris Dearman2006-06-29
| | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Save write-only Config.OD from being clobberedSergei Shtylyov2006-06-05
| | | | | | | | | | Save the Config.OD bit from being clobbered by coherency_setup(). This bit, when set, fixes various errata in the early steppings of Au1x00 SOCs. Unfortunately, the bit was write-only on the most early of them. In addition, also restore the bit after a wakeup from sleep. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Treat R14000 like R10000.Kumba2006-05-31
| | | | | Signed-off-by: Joshua Kinard <kumba@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix deadlock on MP with cache aliases.Ralf Baechle2006-05-31
| | | | | | | | | | | | | A proper fix would involve introducing the notion of shared caches but at this stage of 2.6.17 that's going to be too intrusive and not needed for current hardware; aside I think some discussion will be needed. So for now on the affected SMP configurations which happen to suffer from cache aliases we make use of the fact that a single cache will be shared by all processors. This solves the deadlock issue and will improve performance by getting rid of the smp_call_function overhead. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add missing 34K processor IDsNigel Stephens2006-05-31
| | | | | | The 34K is very much like a 24K on steroids. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Use __ffs() instead of ffs() for waybit calculation.Atsushi Nemoto2006-04-18
| | | | | Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Handle IDE PIO cache aliases on SMP.Ralf Baechle2006-04-18
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix tx49_blast_icache32_page_indexed.Atsushi Nemoto2006-04-18
| | | | | | | | Fix the cache index value in tx49_blast_icache32_page_indexed(). This is a damage by de62893bc0725f8b5f0445250577cd7a10b2d8f8 commit. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] TX49XX has prefetch.Atsushi Nemoto2006-03-21
| | | | | | | | | | The TX49XX has the prefetch instruction. It supports only Pref_Load (hint 0). Actually changes in this patch except for Kconfig are not have any effects, I added these changes to prevent misuse of unsupported hints. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] local_r4k_flush_cache_page fixAtsushi Nemoto2006-03-18
| | | | | | | | | | If dcache_size != icache_size or dcache_size != scache_size, or set-associative cache, icache/scache does not flushed properly. Make blast_?cache_page_indexed() masks its index value correctly. Also, use physical address for physically indexed pcache/scache. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Initialize S-cache function pointers even on S-cache-less CPUs.Ralf Baechle2006-02-28
| | | | | | | | | | | | When a CPU has no scache, the scache flushing functions currently aren't getting initialized and the NULL pointer is eventually called as a function. Initialize the scache flushing functions as a noop when there's no scache. Initial patch by me and most of the debugging done by Martin Michlmayr. Signed-off-by: Martin Michlmayr <tbm@cyrius.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add protected_blast_icache_range, blast_icache_range, etc.Atsushi Nemoto2006-02-14
| | | | | | | | | | Add blast_xxx_range(), protected_blast_xxx_range() etc. for common use. They are built by __BUILD_BLAST_CACHE_RANGE(). Use protected_cache_op() macro for various protected_ routines. Output code should be logically same. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Remove wrong __user tags.Atsushi Nemoto2006-02-07
| | | | | | | This fixes sparse warnings 'dereference of noderef expression'. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.Ralf Baechle2006-01-10
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Rename page argument of flush_cache_page to something more descriptive.Ralf Baechle2005-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Cleanup the mess in cpu_cache_init.Ralf Baechle2005-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Add/Fix missing bit of R4600 hit cacheop workaround.Thiemo Seufer2005-10-29
| | | | | Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Minor code cleanup.Thiemo Seufer2005-10-29
| | | | | Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* More .set push/pop.Thiemo Seufer2005-10-29
| | | | | Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Let r4600 PRID detection match only legacy CPUs, cleanups.Thiemo Seufer2005-10-29
| | | | | Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Avoid SMP cacheflushes. This is a minor optimization of startup butRalf Baechle2005-10-29
| | | | | | | will also avoid smp_call_function from doing stupid things when called from a CPU that is not yet marked online. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* More AP / SP bits for the 34K, the Malta bits and things. Still wantsRalf Baechle2005-10-29
| | | | | | a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Mark a few variables __read_mostly.Ralf Baechle2005-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS R2 instruction hazard handling.Ralf Baechle2005-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Better interface to run uncached cache setup code.Thiemo Seufer2005-10-29
| | | | | Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Sparseify MIPS.Ralf Baechle2005-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Base Au1200 2.6 support.Pete Popov2005-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Use intermediate variable.Thiemo Seufer2005-10-29
| | | | | Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Moves a test which determines if we actually need to perform aRalf Baechle2005-10-29
| | | | | | | cacheflush to the right place. That's a bug which is harmless on UP but a severe bug on SMP. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Update MIPS to use the 4-level pagetable code thereby getting rid ofRalf Baechle2005-10-29
| | | | | | the compacrapability headers. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* 25Kf is also physically indexed.Ralf Baechle2005-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* 20Kc and SB1 don't suffer from aliases.Ralf Baechle2005-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Move missplaced code line to the right place.Ralf Baechle2005-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Use hardware mechanism to deal with cache aliases in the 24K.Ralf Baechle2005-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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