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* [MIPS] vr41xx: Replace magic number for P4K bit with symbol.Yoichi Yuasa2006-07-13
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] vr41xx: Changed workaround to recommended methodYoichi Yuasa2006-07-13
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] VR41xx: Set VR41_CONF_BP only for PrId 0x0c80.Yoichi Yuasa2006-07-13
| | | | | Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Use the proper technical term for naming some of the cache macros.Ralf Baechle2006-07-13
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Remove obsolete #include <linux/config.h>Jörn Engel2006-06-30
| | | | | Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
* [MIPS] 74K: Assume it will also have an AR bit in config7Ralf Baechle2006-06-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Treat CPUs with AR bit as physically indexed.Ralf Baechle2006-06-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix handling of 0 length I & D caches.Chris Dearman2006-06-29
| | | | | | | Don't ask. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] MIPS32/MIPS64 secondary cache managementChris Dearman2006-06-29
| | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Save write-only Config.OD from being clobberedSergei Shtylyov2006-06-05
| | | | | | | | | | Save the Config.OD bit from being clobbered by coherency_setup(). This bit, when set, fixes various errata in the early steppings of Au1x00 SOCs. Unfortunately, the bit was write-only on the most early of them. In addition, also restore the bit after a wakeup from sleep. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Treat R14000 like R10000.Kumba2006-05-31
| | | | | Signed-off-by: Joshua Kinard <kumba@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix deadlock on MP with cache aliases.Ralf Baechle2006-05-31
| | | | | | | | | | | | | A proper fix would involve introducing the notion of shared caches but at this stage of 2.6.17 that's going to be too intrusive and not needed for current hardware; aside I think some discussion will be needed. So for now on the affected SMP configurations which happen to suffer from cache aliases we make use of the fact that a single cache will be shared by all processors. This solves the deadlock issue and will improve performance by getting rid of the smp_call_function overhead. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add missing 34K processor IDsNigel Stephens2006-05-31
| | | | | | The 34K is very much like a 24K on steroids. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Use __ffs() instead of ffs() for waybit calculation.Atsushi Nemoto2006-04-18
| | | | | Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Handle IDE PIO cache aliases on SMP.Ralf Baechle2006-04-18
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix tx49_blast_icache32_page_indexed.Atsushi Nemoto2006-04-18
| | | | | | | | Fix the cache index value in tx49_blast_icache32_page_indexed(). This is a damage by de62893bc0725f8b5f0445250577cd7a10b2d8f8 commit. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] TX49XX has prefetch.Atsushi Nemoto2006-03-21
| | | | | | | | | | The TX49XX has the prefetch instruction. It supports only Pref_Load (hint 0). Actually changes in this patch except for Kconfig are not have any effects, I added these changes to prevent misuse of unsupported hints. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] local_r4k_flush_cache_page fixAtsushi Nemoto2006-03-18
| | | | | | | | | | If dcache_size != icache_size or dcache_size != scache_size, or set-associative cache, icache/scache does not flushed properly. Make blast_?cache_page_indexed() masks its index value correctly. Also, use physical address for physically indexed pcache/scache. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Initialize S-cache function pointers even on S-cache-less CPUs.Ralf Baechle2006-02-28
| | | | | | | | | | | | When a CPU has no scache, the scache flushing functions currently aren't getting initialized and the NULL pointer is eventually called as a function. Initialize the scache flushing functions as a noop when there's no scache. Initial patch by me and most of the debugging done by Martin Michlmayr. Signed-off-by: Martin Michlmayr <tbm@cyrius.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add protected_blast_icache_range, blast_icache_range, etc.Atsushi Nemoto2006-02-14
| | | | | | | | | | Add blast_xxx_range(), protected_blast_xxx_range() etc. for common use. They are built by __BUILD_BLAST_CACHE_RANGE(). Use protected_cache_op() macro for various protected_ routines. Output code should be logically same. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Remove wrong __user tags.Atsushi Nemoto2006-02-07
| | | | | | | This fixes sparse warnings 'dereference of noderef expression'. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.Ralf Baechle2006-01-10
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Rename page argument of flush_cache_page to something more descriptive.Ralf Baechle2005-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Cleanup the mess in cpu_cache_init.Ralf Baechle2005-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Add/Fix missing bit of R4600 hit cacheop workaround.Thiemo Seufer2005-10-29
| | | | | Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Minor code cleanup.Thiemo Seufer2005-10-29
| | | | | Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* More .set push/pop.Thiemo Seufer2005-10-29
| | | | | Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Let r4600 PRID detection match only legacy CPUs, cleanups.Thiemo Seufer2005-10-29
| | | | | Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Avoid SMP cacheflushes. This is a minor optimization of startup butRalf Baechle2005-10-29
| | | | | | | will also avoid smp_call_function from doing stupid things when called from a CPU that is not yet marked online. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* More AP / SP bits for the 34K, the Malta bits and things. Still wantsRalf Baechle2005-10-29
| | | | | | a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Mark a few variables __read_mostly.Ralf Baechle2005-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS R2 instruction hazard handling.Ralf Baechle2005-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Better interface to run uncached cache setup code.Thiemo Seufer2005-10-29
| | | | | Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Sparseify MIPS.Ralf Baechle2005-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Base Au1200 2.6 support.Pete Popov2005-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Use intermediate variable.Thiemo Seufer2005-10-29
| | | | | Signed-off-by: Thiemo Seufer <ths@networkno.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Moves a test which determines if we actually need to perform aRalf Baechle2005-10-29
| | | | | | | cacheflush to the right place. That's a bug which is harmless on UP but a severe bug on SMP. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Update MIPS to use the 4-level pagetable code thereby getting rid ofRalf Baechle2005-10-29
| | | | | | the compacrapability headers. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* 25Kf is also physically indexed.Ralf Baechle2005-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* 20Kc and SB1 don't suffer from aliases.Ralf Baechle2005-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Move missplaced code line to the right place.Ralf Baechle2005-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Use hardware mechanism to deal with cache aliases in the 24K.Ralf Baechle2005-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Remove old wrong bits of cache code.Ralf Baechle2005-10-29
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [PATCH] mips: nuke trailing whitespaceRalf Baechle2005-09-05
| | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] mips: clean up 32/64-bit configurationRalf Baechle2005-09-05
| | | | | | | | Start cleaning 32-bit vs. 64-bit configuration. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-16
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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