| Commit message (Expand) | Author | Age |
* | Rename page argument of flush_cache_page to something more descriptive. | Ralf Baechle | 2005-10-29 |
* | Cleanup the mess in cpu_cache_init. | Ralf Baechle | 2005-10-29 |
* | Add/Fix missing bit of R4600 hit cacheop workaround. | Thiemo Seufer | 2005-10-29 |
* | Minor code cleanup. | Thiemo Seufer | 2005-10-29 |
* | More .set push/pop. | Thiemo Seufer | 2005-10-29 |
* | Let r4600 PRID detection match only legacy CPUs, cleanups. | Thiemo Seufer | 2005-10-29 |
* | Avoid SMP cacheflushes. This is a minor optimization of startup but | Ralf Baechle | 2005-10-29 |
* | More AP / SP bits for the 34K, the Malta bits and things. Still wants | Ralf Baechle | 2005-10-29 |
* | Mark a few variables __read_mostly. | Ralf Baechle | 2005-10-29 |
* | MIPS R2 instruction hazard handling. | Ralf Baechle | 2005-10-29 |
* | Better interface to run uncached cache setup code. | Thiemo Seufer | 2005-10-29 |
* | Sparseify MIPS. | Ralf Baechle | 2005-10-29 |
* | Base Au1200 2.6 support. | Pete Popov | 2005-10-29 |
* | Use intermediate variable. | Thiemo Seufer | 2005-10-29 |
* | Moves a test which determines if we actually need to perform a | Ralf Baechle | 2005-10-29 |
* | Update MIPS to use the 4-level pagetable code thereby getting rid of | Ralf Baechle | 2005-10-29 |
* | 25Kf is also physically indexed. | Ralf Baechle | 2005-10-29 |
* | 20Kc and SB1 don't suffer from aliases. | Ralf Baechle | 2005-10-29 |
* | Move missplaced code line to the right place. | Ralf Baechle | 2005-10-29 |
* | Use hardware mechanism to deal with cache aliases in the 24K. | Ralf Baechle | 2005-10-29 |
* | Remove old wrong bits of cache code. | Ralf Baechle | 2005-10-29 |
* | [PATCH] mips: nuke trailing whitespace | Ralf Baechle | 2005-09-05 |
* | [PATCH] mips: clean up 32/64-bit configuration | Ralf Baechle | 2005-09-05 |
* | Linux-2.6.12-rc2v2.6.12-rc2 | Linus Torvalds | 2005-04-16 |