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path: root/arch/mips/mm/c-r4k.c
Commit message (Expand)AuthorAge
* Rename page argument of flush_cache_page to something more descriptive.Ralf Baechle2005-10-29
* Cleanup the mess in cpu_cache_init.Ralf Baechle2005-10-29
* Add/Fix missing bit of R4600 hit cacheop workaround.Thiemo Seufer2005-10-29
* Minor code cleanup.Thiemo Seufer2005-10-29
* More .set push/pop.Thiemo Seufer2005-10-29
* Let r4600 PRID detection match only legacy CPUs, cleanups.Thiemo Seufer2005-10-29
* Avoid SMP cacheflushes. This is a minor optimization of startup butRalf Baechle2005-10-29
* More AP / SP bits for the 34K, the Malta bits and things. Still wantsRalf Baechle2005-10-29
* Mark a few variables __read_mostly.Ralf Baechle2005-10-29
* MIPS R2 instruction hazard handling.Ralf Baechle2005-10-29
* Better interface to run uncached cache setup code.Thiemo Seufer2005-10-29
* Sparseify MIPS.Ralf Baechle2005-10-29
* Base Au1200 2.6 support.Pete Popov2005-10-29
* Use intermediate variable.Thiemo Seufer2005-10-29
* Moves a test which determines if we actually need to perform aRalf Baechle2005-10-29
* Update MIPS to use the 4-level pagetable code thereby getting rid ofRalf Baechle2005-10-29
* 25Kf is also physically indexed.Ralf Baechle2005-10-29
* 20Kc and SB1 don't suffer from aliases.Ralf Baechle2005-10-29
* Move missplaced code line to the right place.Ralf Baechle2005-10-29
* Use hardware mechanism to deal with cache aliases in the 24K.Ralf Baechle2005-10-29
* Remove old wrong bits of cache code.Ralf Baechle2005-10-29
* [PATCH] mips: nuke trailing whitespaceRalf Baechle2005-09-05
* [PATCH] mips: clean up 32/64-bit configurationRalf Baechle2005-09-05
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-16
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