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Commit message (Expand)AuthorAge
* [MIPS] Reimplement clear_page/copy_pageThiemo Seufer2008-04-28
* [MIPS] Split the micro-assembler from tlbex.c.Thiemo Seufer2008-02-01
* [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.Ralf Baechle2007-10-11
* [MIPS] Use -Werror on subdirectories which build cleanly.Ralf Baechle2007-07-31
* [MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2Fuxin Zhang2007-07-10
* [MIPS] Kill redundant EXTRA_AFLAGSAtsushi Nemoto2007-02-26
* [MIPS] Unify dma-{coherent,noncoherent.ip27,ip32}Ralf Baechle2007-02-13
* [MIPS] MIPS32/MIPS64 secondary cache managementChris Dearman2006-06-29
* [MIPS] Kill tlb-andes.c.Thiemo Seufer2006-03-21
* Fixup a few lose ends in explicit support for MIPS R1/R2.Ralf Baechle2005-10-29
* Use R4000 TLB routines for SB1 also.Ralf Baechle2005-10-29
* Rename CONFIG_CPU_MIPS{32,64} to CONFIG_CPU_MIPS{32|64}_R1.Ralf Baechle2005-10-29
* [PATCH] mips: clean up 32/64-bit configurationRalf Baechle2005-09-05
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-16
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