| Commit message (Collapse) | Author | Age |
|---|
| |
|
|
|
|
|
|
|
| |
This code makes the irqs used by the EIU loadable from the DT. Additionally we
add a helper that allows the pinctrl layer to map external irqs to real irq
numbers.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4818/
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The introduction of the OF support broke the cp0_perfcount_irq mapping. This
resulted in oprofile not working anymore.
Offending commit is :
commit 3645da0276ae9f6938ff29b13904b803ecb68424
Author: John Crispin <blogic@openwrt.org>
Date: Tue Apr 17 10:18:32 2012 +0200
OF: MIPS: lantiq: implement irq_domain support
Signed-off-by: Conor O'Gorman <i@conorogorman.net>
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4875/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
|
|
|
|
| |
Support for the external interrupt unit was broken when the code was converted
to devicetree support.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4231/
|
| |
|
|
|
|
|
| |
We dont want to register the irq_chip for the MIPS IRQ cascade.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4230/
|
| |
|
|
|
|
|
|
| |
The SVIP SoC has its timer IRQ on a different IRQ than 7. Fix up the irq
code to be able to handle this.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4229/
|
| |
|
|
|
|
|
|
| |
Up to now all our SoCs had the 5 IM ranges in a consecutive order. To accomodate
the SVIP we need to support IM ranges that are scattered inside the register range.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4237/
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add support for irq_domain on lantiq socs. The conversion is straight forward
as the ICU found inside the socs allows the usage of irq_domain_add_linear.
Harware IRQ 0->7 are the generic MIPS IRQs. 8->199 are the Lantiq IRQ Modules.
Our irq_chip callbacks need to substract 8 (MIPS_CPU_IRQ_CASCADE) from d->hwirq
to find out the correct offset into the Interrupt Modules register range.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: devicetree-discuss@lists.ozlabs.org
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3802/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
|
|
|
|
|
|
| |
Add IPI handlers to the interrupt code. This patch makes MIPS_MT_SMP work
on lantiq socs. The code is based on the malta implementation.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3704/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
|
|
|
|
|
| |
This patch sets the performance counters irq on Lantiq SoCs.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3720/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
|
|
|
|
|
| |
Due to missing brackets, the irq modules were not properly reset on boot.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3719/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |\ |
|
| | |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Since commit [e58aa3d2: genirq: Run irq handlers with interrupts disabled],
We run all interrupt handlers with interrupts disabled and we even check
and yell when an interrupt handler returns with interrupts enabled (see
commit [b738a50a: genirq: Warn when handler enables interrupts]).
So now this flag is a NOOP and can be removed.
[ralf@linux-mips.org: Fixed up conflicts in
arch/mips/alchemy/common/dbdma.c, arch/mips/cavium-octeon/smp.c and
arch/mips/kernel/perf_event.c.]
Signed-off-by: Yong Zhang <yong.zhang0@gmail.com>
To: linux-kernel@vger.kernel.org
Cc: tglx@linutronix.de
linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2835/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |/
|
|
|
|
|
|
| |
Panic() invokes printk() to add a \n internally, so panic arguments should
not themselves end in \n. Panic invocations in arch/mips and elsewhere
are inconsistently sometimes terminating in \n, sometimes not.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
|
|
|
|
|
|
|
| |
The irq base offset needs to be ignored when matching irqs to external
interrupt pins. Taking the offset into account resulted in the EIU not
being brought up properly.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2616/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
|
|
Add initial support for Mips based SoCs made by Lantiq. This series will add
support for the XWAY family.
The series allows booting a minimal system using a initramfs or NOR. Missing
drivers and support for Amazon and GPON family will be provided in a later
series.
[Ralf: Remove some cargo cult programming and fixed formatting.]
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2252/
Patchwork: https://patchwork.linux-mips.org/patch/2371/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
