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* Merge tag 'devicetree-for-3.13' of ↵Linus Torvalds2013-11-12
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree updates from Rob Herring: "DeviceTree updates for 3.13. This is a bit larger pull request than usual for this cycle with lots of clean-up. - Cross arch clean-up and consolidation of early DT scanning code. - Clean-up and removal of arch prom.h headers. Makes arch specific prom.h optional on all but Sparc. - Addition of interrupts-extended property for devices connected to multiple interrupt controllers. - Refactoring of DT interrupt parsing code in preparation for deferred probe of interrupts. - ARM cpu and cpu topology bindings documentation. - Various DT vendor binding documentation updates" * tag 'devicetree-for-3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (82 commits) powerpc: add missing explicit OF includes for ppc dt/irq: add empty of_irq_count for !OF_IRQ dt: disable self-tests for !OF_IRQ of: irq: Fix interrupt-map entry matching MIPS: Netlogic: replace early_init_devtree() call of: Add Panasonic Corporation vendor prefix of: Add Chunghwa Picture Tubes Ltd. vendor prefix of: Add AU Optronics Corporation vendor prefix of/irq: Fix potential buffer overflow of/irq: Fix bug in interrupt parsing refactor. of: set dma_mask to point to coherent_dma_mask of: add vendor prefix for PHYTEC Messtechnik GmbH DT: sort vendor-prefixes.txt of: Add vendor prefix for Cadence of: Add empty for_each_available_child_of_node() macro definition arm/versatile: Fix versatile irq specifications. of/irq: create interrupts-extended property microblaze/pci: Drop PowerPC-ism from irq parsing of/irq: Create of_irq_parse_and_map_pci() to consolidate arch code. of/irq: Use irq_of_parse_and_map() ...
| * Merge remote-tracking branch 'grant/devicetree/next' into for-nextRob Herring2013-11-07
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| * | MIPS: Netlogic: replace early_init_devtree() callJayachandran C2013-11-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The early_init_devtree() API was removed in linux-next for 3.13 with commit "mips: use early_init_dt_scan". This causes Netlogic XLP compile to fail: arch/mips/netlogic/xlp/setup.c:101: undefined reference to `early_init_devtree' Add xlp_early_init_devtree() which uses the __dt_setup_arch() to handle early device tree related initialization to fix this. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| * | of: implement pci_address_to_pio as weak functionRob Herring2013-10-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement pci_address_to_pio as weak function to remove the dependency on asm/prom.h. This is in preparation to make prom.h optional. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Grant Likely <grant.likely@linaro.org> Cc: Michal Simek <monstr@monstr.eu> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: x86@kernel.org Cc: Grant Likely <grant.likely@linaro.org>
| * | mips: use early_init_dt_scanRob Herring2013-10-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert mips to use new early_init_dt_scan function. Remove early_init_dt_scan_memory_arch Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Acked-by: John Crispin <blogic@openwrt.org>
* | | Merge branch 'sched-core-for-linus' of ↵Linus Torvalds2013-11-11
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull scheduler changes from Ingo Molnar: "The main changes in this cycle are: - (much) improved CONFIG_NUMA_BALANCING support from Mel Gorman, Rik van Riel, Peter Zijlstra et al. Yay! - optimize preemption counter handling: merge the NEED_RESCHED flag into the preempt_count variable, by Peter Zijlstra. - wait.h fixes and code reorganization from Peter Zijlstra - cfs_bandwidth fixes from Ben Segall - SMP load-balancer cleanups from Peter Zijstra - idle balancer improvements from Jason Low - other fixes and cleanups" * 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (129 commits) ftrace, sched: Add TRACE_FLAG_PREEMPT_RESCHED stop_machine: Fix race between stop_two_cpus() and stop_cpus() sched: Remove unnecessary iteration over sched domains to update nr_busy_cpus sched: Fix asymmetric scheduling for POWER7 sched: Move completion code from core.c to completion.c sched: Move wait code from core.c to wait.c sched: Move wait.c into kernel/sched/ sched/wait: Fix __wait_event_interruptible_lock_irq_timeout() sched: Avoid throttle_cfs_rq() racing with period_timer stopping sched: Guarantee new group-entities always have weight sched: Fix hrtimer_cancel()/rq->lock deadlock sched: Fix cfs_bandwidth misuse of hrtimer_expires_remaining sched: Fix race on toggling cfs_bandwidth_used sched: Remove extra put_online_cpus() inside sched_setaffinity() sched/rt: Fix task_tick_rt() comment sched/wait: Fix build breakage sched/wait: Introduce prepare_to_wait_event() sched/wait: Add ___wait_cond_timeout() to wait_event*_timeout() too sched: Remove get_online_cpus() usage sched: Fix race in migrate_swap_stop() ...
| * \ \ Merge branch 'core/urgent' into sched/coreIngo Molnar2013-10-11
| |\ \ \ | | | |/ | | |/| | | | | | | | | | | | | Merge in asm goto fix, to be able to apply the asm/rmwcc.h fix. Signed-off-by: Ingo Molnar <mingo@kernel.org>
| * | | Merge tag 'v3.12-rc4' into sched/coreIngo Molnar2013-10-09
| |\ \ \ | | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge Linux v3.12-rc4 to fix a conflict and also to refresh the tree before applying more scheduler patches. Conflicts: arch/avr32/include/asm/Kbuild Signed-off-by: Ingo Molnar <mingo@kernel.org>
| * | | sched, arch: Create asm/preempt.hPeter Zijlstra2013-09-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to prepare to per-arch implementations of preempt_count move the required bits into an asm-generic header and use this for all archs. Signed-off-by: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/n/tip-h5j0c1r3e3fk015m30h8f1zx@git.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
* | | | MIPS: Random whitespace clean-upsMaciej W. Rozycki2013-11-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Another whitespace clean-up, this removes tabs from between sentences in some comments. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6103/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | MIPS: Remove unused defines in piix4.hDeng-Cheng Zhu2013-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PIIX4_ICTLR* and PIIX4_OCW* defines are not used by any other files. Remove them. The only file (other than fixup-malta.c which includes piix4.h in patch #1) containing "#include <asm/mips-boards/piix4.h>" is arch/mips/mti-malta/malta-int.c whose first version is actually "1da177e4c3:arch/mips/mips-boards/malta/malta_int.c". In that version, in the function get_int(), things in piix4.h are used. But now malta-int.c no longer needs those stuff. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6032/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | MIPS: Get rid of hard-coded values for Malta PIIX4 fixupsDeng-Cheng Zhu2013-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the code more readable by using defines. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6031/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | MIPS: Always register R4K clock when selectedSteven J. Hill2013-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Always register the R4K clocksource when CONFIG_CSRC_R4K is selected, regardless of selected support for other clocksources. The kernel will select the best clocksource based on their ratings, making it safe to register R4K unconditionally and use it as a fallback should the kernel be run on a system where other selected clocksources are inoperable. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6024/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over arch/mips.Ralf Baechle2013-10-29
| | | | | | | | | | | | | | | | | | | | | | | | It was ugly. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | MIPS: cacheops.h: Increase indentation by one tab.Ralf Baechle2013-10-29
| | | | | | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | MIPS: PowerTV: Remove support code.Ralf Baechle2013-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nobody seems to care about this platform anymore and my attempts to find somebody willing to provide some tlc for PowerTV have failed so far. So let's nuke the bloody thing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/5910/
* | | | MIPS: ftrace: Add support for syscall tracepoints.Ralf Baechle2013-10-29
| | | | | | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | MIPS: Move audit_arch() helper function to __syscall_get_arch().Ralf Baechle2013-10-29
| | | | | | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | MIPS: Enable HAVE_ARCH_TRACEHOOK.Ralf Baechle2013-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables /proc/<pid>/syscall and the ptrace PTRACE_GETREGSET and PTRACE_SETREGSET operations. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | MIPS: Switch ELF core dumper to use regsets.Ralf Baechle2013-10-29
| | | | | | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | MIPS: Provide arch_syscall_addr.Ralf Baechle2013-10-29
| | | | | | | | | | | | | | | | | | | | | | | | The generic version is wrong for MIPS. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | MIPS: Enable entries for SIGSYS in struct siginfo.Ralf Baechle2013-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is necessary because MIPS doesn't use HAVE_ARCH_SIGINFO_T for historical reasons. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXTJayachandran C2013-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow usage of scratch register for current pgd even when MIPS_PGD_C0_CONTEXT is not configured. MIPS_PGD_C0_CONTEXT is set for 64r2 platforms to indicate availability of Xcontext for saving cpuid, thus freeing Context to be used for saving PGD. This option was also tied to using a scratch register for storing PGD. This commit will allow usage of scratch register to store the current pgd if one can be allocated for the platform, even when MIPS_PGD_C0_CONTEXT is not set. The cpuid will be kept in the CP0 Context register in this case. The code to store the current pgd for the TLB miss handler is now generated in all cases. When scratch register is available, the PGD is also stored in the scratch register. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/5906/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | MIPS: DECstation CPU feature overridesMaciej W. Rozycki2013-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5877/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | DEC: Whitespace cleanupMaciej W. Rozycki2013-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 7034228792cc561e79ff8600f02884bd4c80e287 [MIPS: Whitespace cleanup.] did a lot of good and a little damage. Revert the damage. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5875/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | MIPS: DECstation I/O ASIC DMA interrupt classesMaciej W. Rozycki2013-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change complements commits d0da7c002f7b2a93582187a9e3f73891a01d8ee4 [MIPS: DEC: Convert to new irq_chip functions] and 5359b938c088423a28c41499f183cd10824c1816 [MIPS: DECstation I/O ASIC DMA interrupt handling fix] and implements automatic handling of the two classes of DMA interrupts the I/O ASIC implements, informational and errors. Informational DMA interrupts do not stop the transfer and use the `handle_edge_irq' handler that clears the request right away so that another request may be recorded while the previous is being handled. DMA error interrupts stop the transfer and require a corrective action before DMA can be reenabled. Therefore they use the `handle_fasteoi_irq' handler that only clears the request on the way out. Because MIPS processor interrupt inputs, one of which the I/O ASIC's interrupt controller is cascaded to, are level-triggered it is recommended that error DMA interrupt action handlers are registered with the IRQF_ONESHOT flag set so that they are run with the interrupt line masked. This change removes the export of clear_ioasic_dma_irq that now does not have to be called by device drivers to clear interrupts explicitly anymore. Originally these interrupts were cleared in the .end handler of the `irq_chip' structure, before it was removed. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5874/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | MIPS: Remove unnecessary platform dma helper functionsFelix Fietkau2013-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The semantics stay the same - on Cavium Octeon the functions were dead code (it overrides the MIPS DMA ops) - on other platforms they contained no code at all. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5720/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | MIPS: Add 8250/16550 serial early printk driverYoichi Yuasa2013-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/947/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | MIPS: BCM47XX: Get GPIO pin from nvram configurationHauke Mehrtens2013-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The nvram contains some gpio configuration for boards. It is stored in a gpio<number>=name format e.g. gpio8=wps_button gpio4=robo_reset This patches adds a function to parse these entries, so other driver can use it. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5841/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | MIPS: BCM47XX: Add board detectionHauke Mehrtens2013-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Detect on which board this code is running based on some nvram settings. This is needed to start board specific workarounds and configure the leds and buttons which are on different gpios on every board. This patches add some boards we have seen, but there are many more. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5840 Patchwork: https://patchwork.linux-mips.org/patch/5855/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | MIPS: Move definition of SMP processor id register to header fileJayachandran C2013-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The definition of the CP0 register used to save the smp processor id is repicated in many files, move them all to thread_info.h. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5708/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | MIPS: ath79: Remove ar933x_uart_platform.h headerGabor Juhos2013-10-29
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit 15ef17f622033455dcf03ae96256e474073a7b11 (tty: ar933x_uart: use the clk API to get the uart clock), the AR933x UART driver for has been converted to get the uart clock rate via the clock API and it does not use the platform data anymore. Remove the ar933x_uart_platform.h header file and get rid of the superfluous variable and initialization code in platform setup. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5832/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | compiler/gcc4: Add quirk for 'asm goto' miscompilation bugIngo Molnar2013-10-11
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fengguang Wu, Oleg Nesterov and Peter Zijlstra tracked down a kernel crash to a GCC bug: GCC miscompiles certain 'asm goto' constructs, as outlined here: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670 Implement a workaround suggested by Jakub Jelinek. Reported-and-tested-by: Fengguang Wu <fengguang.wu@intel.com> Reported-by: Oleg Nesterov <oleg@redhat.com> Reported-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Suggested-by: Jakub Jelinek <jakub@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: <stable@kernel.org> Signed-off-by: Ingo Molnar <mingo@kernel.org>
* | MIPS: cpu-features.h: s/MIPS53/MIPS64/Maciej W. Rozycki2013-09-24
| | | | | | | | | | | | | | | | | | No support for MIPS53 processors yet. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5876/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Add MIPS R5 config5 register.Ralf Baechle2013-09-19
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: PCI: Use pci_resource_to_user to map pci memory space properlyWolfgang Grandegger2013-09-18
| | | | | | | | | | | | | | | | | | | | | | [ralf@linux-mips.org: This only matters to Alchemy platforms. On other platforms fixup_bigphys_addr is just an identidy mapping.] Signed-off-by: Wolfgang Grandegger <wg@denx.de> Cc: tiejun.chen <tiejun.chen@windriver.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/1868/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Cleanup CP0 PRId and CP1 FPIR register access masksMaciej W. Rozycki2013-09-18
| | | | | | | | | | | | | | | | | | | | Replace hardcoded CP0 PRId and CP1 FPIR register access masks throughout. The change does not touch places that use shifted or partial masks. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5838/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Fix VGA_MAP_MEM macro.Leonid Yegoshin2013-09-18
| | | | | | | | | | | | | | | | | | | | | | | | Use the CKSEG1ADDR macro when calculating VGA_MAP_MEM. [ralf@linux-mips.org: Include <asm/addrspace.h for CKSEG1ADDR.] Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5814/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Reimplement get_cycles().Ralf Baechle2013-09-18
| | | | | | | | | | | | | | | | | | | | | | | | | | This essentially reverts commit efb9ca08b5a2374b29938cdcab417ce4feb14b54 (kernel.org) / 58020a106879a8b372068741c81f0015c9b0b96dbv [[MIPS] Change get_cycles to always return 0.] Most users of get_cycles() invoke it as a timing interface. That's why in modern kernels it was never very much missed for. /dev/random however uses get_cycles() in the how the jitter in the interrupt timing contains some useful entropy. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Optimize current_cpu_type() for better code.Ralf Baechle2013-09-17
| | | | | | | | | | | | | | | | | | | | | | | | | | o Move current_cpu_type() to a separate header file o #ifdefing on supported CPU types lets modern GCC know that certain code in callers may be discarded ideally turning current_cpu_type() into a function returning a constant. o Use current_cpu_type() rather than direct access to struct cpuinfo_mips. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5833/
* | MIPS: Provide nice way to access boot CPU's data.Ralf Baechle2013-09-17
|/ | | | | | | | boot_cpu_data is used the same as current_cpu_data but returns the CPU data for CPU 0. This means it doesn't have to use smp_processor_id() thus no need to disable preemption. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: DECstation I/O ASIC DMA interrupt handling fixMaciej W. Rozycki2013-09-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | This change complements commit d0da7c002f7b2a93582187a9e3f73891a01d8ee4 and brings clear_ioasic_irq back, renaming it to clear_ioasic_dma_irq at the same time, to make I/O ASIC DMA interrupts functional. Unlike ordinary I/O ASIC interrupts DMA interrupts need to be deasserted by software by writing 0 to the respective bit in I/O ASIC's System Interrupt Register (SIR), similarly to how CP0.Cause.IP0 and CP0.Cause.IP1 bits are handled in the CPU (the difference is SIR DMA interrupt bits are R/W0C so there's no need for an RMW cycle). Otherwise the handler is reentered over and over again. The only current user is the DEC LANCE Ethernet driver and its extremely uncommon DMA memory error handler that does not care when exactly the interrupt is cleared. Anticipating the use of DMA interrupts by the Zilog SCC driver this change however exports clear_ioasic_dma_irq for device drivers to choose the right application-specific sequence to clear the request explicitly rather than calling it implicitly in the .irq_eoi handler of `struct irq_chip'. Previously these interrupts were cleared in the .end handler of the said structure, before it was removed. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5826/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: DECstation HRT initialization rearrangementMaciej W. Rozycki2013-09-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all I/O ASIC versions have the free-running counter implemented, an early revision used in the 5000/1xx models aka 3MIN and 4MIN did not have it. Therefore we cannot unconditionally use it as a clock source. Fortunately if not implemented its register slot has a fixed value so it is enough if we check for the value at the end of the calibration period being the same as at the beginning. This also means we need to look for another high-precision clock source on the systems affected. The 5000/1xx can have an R4000SC processor installed where the CP0 Count register can be used as a clock source. Unfortunately all the R4k DECstations suffer from the missed timer interrupt on CP0 Count reads erratum, so we cannot use the CP0 timer as a clock source and a clock event both at a time. However we never need an R4k clock event device because all DECstations have a DS1287A RTC chip whose periodic interrupt can be used as a clock source. This gives us the following four configuration possibilities for I/O ASIC DECstations: 1. No I/O ASIC counter and no CP0 timer, e.g. R3k 5000/1xx (3MIN). 2. No I/O ASIC counter but the CP0 timer, i.e. R4k 5000/150 (4MIN). 3. The I/O ASIC counter but no CP0 timer, e.g. R3k 5000/240 (3MAX+). 4. The I/O ASIC counter and the CP0 timer, e.g. R4k 5000/260 (4MAX+). For #1 and #2 this change stops the I/O ASIC free-running counter from being installed as a clock source of a 0Hz frequency. For #2 it also arranges for the CP0 timer to be used as a clock source rather than a clock event device, because having an accurate wall clock is more important than a high-precision interval timer. For #3 there is no change. For #4 the change makes the I/O ASIC free-running counter installed as a clock source so that the CP0 timer can be used as a clock event device. Unfortunately the use of the CP0 timer as a clock event device relies on a succesful completion of c0_compare_interrupt. That never happens, because while waiting for a CP0 Compare interrupt to happen the function spins in a loop reading the CP0 Count register. This makes the CP0 Count erratum trigger reliably causing the interrupt waited for to be lost in all cases. As a result #4 resorts to using the CP0 timer as a clock source as well, just as #2. However we want to keep this separate arrangement in case (hope) c0_compare_interrupt is eventually rewritten such that it avoids the erratum. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5825/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2013-09-12
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: "This has been sitting in -next for a while with no objections and all MIPS defconfigs except one are building fine; that one platform got broken by another patch in your tree and I'm going to submit a patch separately. - a handful of fixes that didn't make 3.11 - a few bits of Octeon 3 support with more to come for a later release - platform enhancements for Octeon, ath79, Lantiq, Netlogic and Ralink SOCs - a GPIO driver for the Octeon - some dusting off of the DECstation code - the usual dose of cleanups" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (65 commits) MIPS: DMA: Fix BUG due to smp_processor_id() in preemptible code MIPS: kexec: Fix random crashes while loading crashkernel MIPS: kdump: Skip walking indirection page for crashkernels MIPS: DECstation HRT calibration bug fixes MIPS: Export copy_from_user_page() (needed by lustre) MIPS: Add driver for the built-in PCI controller of the RT3883 SoC MIPS: DMA: For BMIPS5000 cores flush region just like non-coherent R10000 MIPS: ralink: Add support for reset-controller API MIPS: ralink: mt7620: Add cpu-feature-override header MIPS: ralink: mt7620: Add spi clock definition MIPS: ralink: mt7620: Add wdt clock definition MIPS: ralink: mt7620: Improve clock frequency detection MIPS: ralink: mt7620: This SoC has EHCI and OHCI hosts MIPS: ralink: mt7620: Add verbose ram info MIPS: ralink: Probe clocksources from OF MIPS: ralink: Add support for systick timer found on newer ralink SoC MIPS: ralink: Add support for periodic timer irq MIPS: Netlogic: Built-in DTB for XLP2xx SoC boards MIPS: Netlogic: Add support for USB on XLP2xx MIPS: Netlogic: XLP2xx update for I2C controller ...
| * MIPS: ralink: mt7620: Add cpu-feature-override headerGabor Juhos2013-09-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Override certain CPU features to help GCC to optimize the generated code. Saves about 150KB in the vmlinux image with a generic configuration. text data bss dec hex filename 3824158 134820 234192 4193170 3ffb92 vmlinux.no-override 3664054 138804 234192 4037050 3d99ba vmlinux.override Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5759/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: ralink: mt7620: Improve clock frequency detectionGabor Juhos2013-09-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code assumes that the peripheral clock always runs at 40MHz which is not true in all configuration. The peripheral clock can also use the reference clock instead of the fixed 40MHz rate. If the reference clock runs at a different rate, various peripheries are behaving incorrectly. Additionally, the currectly calculated system clock is also wrong. The actual value what the code computes is the rate of the DRAM which can be different from the system clock. Add new helper functions to get the rate of the different clocks and use the correct values for the registered clock devices. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Netlogic: Add support for USB on XLP2xxGanesan Ramalingam2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | Add USB intialization code to handle the new XLP2XX USB 3.0 block. This adds xlp/usb-init-xlp2.c to initialize the XLP2XX USB glue-logic for XHCI and EHCI. Interrupt and IO offset code in xlp-hal/iomap.h and xlp/nlm_hal.c is also updated for the new USB block. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5744/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Netlogic: XLP2xx update for I2C controllerGanesan Ramalingam2013-09-03
| | | | | | | | | | | | | | | | | | | | | | XLP2xx has a new I2C controller which has 4 buses connected to it. Update the IO offset and IRQ mapping code to reflect this. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5707/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Netlogic: XLP2XX CPU and PIC frequencyGanesan Ramalingam2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | Add code to calculate the CPU and PIC frequency for XLP2XX SoCs. Since the PIC frequency on XLP2XX can be configured, add a new macro pic_timer_freq() to be used in netlogic/common/time.c. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Cc: Ganesan Ramalingam <ganesanr@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/5701/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Netlogic: Add support for XLP2XXJayachandran C2013-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | XLP2XX is first in the series of 28nm XLPII processors. The changes are to: * Add processor ID for XLP2XX to asm/cpu.h and kernel/cpu-probe.c. * Add a cpu_is_xlpii() function to check for XLPII processors. * Update xlp_mmu_init() to use config4 to enable extended TLB. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5698/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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