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* MIPS: Allow kernel use of LL/SC to be separate from the presence of LL/SC.David Daney2009-09-17
| | | | | | | | | | | | | | | | | On some CPUs, it is more efficient to disable and enable interrupts in the kernel rather than use ll/sc for atomic operations. But if we were to set cpu_has_llsc to false, we would break the userspace futex interface (in asm/futex.h). We separate the two concepts, with a new predicate kernel_uses_llsc, that lets us disable the kernel's use of ll/sc while still allowing the futex code to use it. Also there were a couple of cases in bitops.h where we were using ll/sc unconditionally even if cpu_has_llsc were false. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Rewrite clearing of ll_bit on context switch in CRalf Baechle2009-09-17
| | | | | | This also means there is now only one implementation not 3 left. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Rewrite sysmips(MIPS_ATOMIC_SET, ...) in C with inline assemblerRalf Baechle2009-09-17
| | | | | | This way it doesn't have to use CONFIG_CPU_HAS_LLSC anymore. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Consolidate all CONFIG_CPU_HAS_LLSC use in a single C file.Ralf Baechle2009-09-17
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Scheduler support for HARDWARE_WATCHPOINTS.David Daney2008-10-11
| | | | | | | | | Here we hook up the scheduler. Whenever we switch to a new process, we check to see if the watch registers should be installed, and do it if needed. Signed-off-by: David Daney <ddaney@avtrex.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Move headfiles to new location below arch/mips/includeRalf Baechle2008-10-11
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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