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path: root/arch/mips/include/asm/mipsregs.h
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* MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQsDavid VomLehn2010-01-27
| | | | | | | | | | | | | | | | | The MIPS processor is limited to 64 external interrupt sources. Using a greater number without IRQ sharing requires reading platform-specific registers. On such platforms, reading the IntCtl register to determine which interrupt corresponds to a timer interrupt will not work. On MIPSR2 systems there is a solution - the TI bit in the Cause register, specifically indicates that a timer interrupt has occured. This patch uses that bit to detect interrupts for MIPSR2 processors, which may be expected to work regardless of how the timer interrupt may be routed in the hardware. Signed-off-by: David VomLehn (dvomlehn@cisco.com) To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/804/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add hugetlbfs page defines.David Daney2009-06-17
| | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix sign-extension bug in 32-bit kernel on 32-bit hardware.Ralf Baechle2009-05-14
| | | | | | | Probably nobody does arithmetic on cp0 register values so this has never bitten. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Cavium: Add support for 8k and 32k page sizes.Ralf Baechle2009-05-14
| | | | | | | | Beyond the requirements of the architecture standard Cavium also supports 8k and 32k pages. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: David Daney <ddaney@caviumnetworks.com>
* MIPS: SMTC: Bring set/clear/change_c0_## return value semantics uptodate.Kevin D. Kissell2009-05-14
| | | | | Signed-off-by: Kevin D. Kissell <kevink@paralogos.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Change {set,clear,change}_c0_<foo> to return old value.Ralf Baechle2009-03-23
| | | | | | | This is more standard and useful and need for the following fix to work correctly. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Override assembler target architecture for octeon.David Daney2009-01-11
| | | | | | | | | Gas from binutils 2.19 fails to compile some cop1 instructions with -march=octeon. Since the cop1 instructions are present in mips1, use that arch instead. This will be fixed in binutils 2.20. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add Cavium OCTEON specific register definitions to mipsregs.hDavid Daney2009-01-11
| | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add CONFIG_CPU_R5500 for NEC VR5500 series processorsShinya Kuribayashi2008-10-27
| | | | | | | | | | | | We already have sufficient infrastructure to support VR5500 and VR5500A series processors. Here's a Makefile support to make it selectable by ports, and enable it for NEC EMMA2RH Markeins board. This patch also fixes a confused target help, and adds 1Gb PageMask bits supported by VR5500 and its variants. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Move headfiles to new location below arch/mips/includeRalf Baechle2008-10-11
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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