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| * | | m68k: create ColdFire MMU pgalloc codeGreg Ungerer2011-12-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add code to support the ColdFire V4e MMU pgalloc functions. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Matt Waddel <mwaddel@yahoo.com> Acked-by: Kurt Mahan <kmahan@xmission.com>
| * | | m68k: ColdFire V4e MMU paging init code and miss handlerGreg Ungerer2011-12-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The different ColdFire V4e MMU requires its own dedicated paging init code, and a TLB miss handler for its software driven TLB. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Matt Waddel <mwaddel@yahoo.com> Acked-by: Kurt Mahan <kmahan@xmission.com>
| * | | m68k: use ColdFire MMU read/write bit flags when ioremappingGreg Ungerer2011-12-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ColdFire MMU has separate read and write bits, unlike the Motorola m68k MMU which has a single read-only bit. Define a _PAGE_READWRITE value for the Motorola MMU, which is 0, so we can unconditionaly include that in the page table entry bits when setting up ioremapped pages. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Matt Waddel <mwaddel@yahoo.com> Acked-by: Kurt Mahan <kmahan@xmission.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
| * | | m68k: ColdFire V4e MMU context support codeGreg Ungerer2011-12-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add code to manage the context's of the ColdFire V4e MMU. This code is mostly taken from the Freescale 2.6.35 kernel BSP for MMU enabled ColdFire. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Matt Waddel <mwaddel@yahoo.com> Acked-by: Kurt Mahan <kmahan@xmission.com>
| * | | m68k: MMU enabled ColdFire needs 8k ELF alignmentGreg Ungerer2011-12-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Like the SUN3 hardware MMU the ColdFire MMU uses 8k pages. So we want our ELF page size alingment to also be 8k. Modify the ELF alignment setting. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Matt Waddel <mwaddel@yahoo.com> Acked-by: Kurt Mahan <kmahan@xmission.com>
| * | | m68k: set ColdFire MMU page sizeGreg Ungerer2011-12-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We use the ColdFire V4e MMU page size of 8KiB. Define PAGE_SHIFT appropriately. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Matt Waddel <mwaddel@yahoo.com> Acked-by: Kurt Mahan <kmahan@xmission.com>
| * | | m68k: define PAGE_OFFSET_RAW for ColdFire CPU with MMU enabledGreg Ungerer2011-12-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ColdFire CPU configurations need PAGE_OFFSET_RAW set to the base of their RAM. It doesn't matter if they are running with the MMU enabled or disabled, it is always set to the base of RAM. We can keep the choices simple here and key of CONFIG_RAMBASE. If it is defined we are on a plaftorm (ColdFire or other non-MMU systems) which have a configurable RAM base, just use it. Reported-by: Alexander Stein <alexander.stein@systec-electronic.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Matt Waddel <mwaddel@yahoo.com> Acked-by: Kurt Mahan <kmahan@xmission.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
| * | | m68k: add TLB flush support for the ColdFire V4e MMU hardwareGreg Ungerer2011-12-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ColdFire V4e MMU is unlike any of the other m68k MMU hardware. It needs its own TLB flush support code. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Matt Waddel <mwaddel@yahoo.com> Acked-by: Kurt Mahan <kmahan@xmission.com>
| * | | m68k: modify ColdFire 54xx cache support for MMU enabledGreg Ungerer2011-12-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify the cache setup for the ColdFire 54xx parts when running with the MMU enabled. We want to map the peripheral register space (MBAR region) as non cacheable. And create an identity mapping for all of RAM for the kernel. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Matt Waddel <mwaddel@yahoo.com> Acked-by: Kurt Mahan <kmahan@xmission.com>
| * | | m68k: add cache support for V4e ColdFire cores running with MMU enabledGreg Ungerer2011-12-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add code to deal with instruction, data and branch caches of the V4e ColdFire cores when they are running with the MMU enabled. This code is loosely based on Freescales changes for the caches of the V4e ColdFire in the 2.6.25 kernel BSP. That code was originally by Kurt Mahan <kmahan@freescale.com> (now <kmahan@xmission.com>). Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Matt Waddel <mwaddel@yahoo.com> Acked-by: Kurt Mahan <kmahan@xmission.com>
| * | | m68k: add page table size definitions for ColdFire V4e MMUGreg Ungerer2011-12-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define the page table size and attributes for the ColdFire V4e MMU. Also setup the vmalloc and kmap regions we will use. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Matt Waddel <mwaddel@yahoo.com> Acked-by: Kurt Mahan <kmahan@xmission.com>
| * | | m68k: page table support definitions and code for ColdFire MMUGreg Ungerer2011-12-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ColdFire V4e MMU is nothing like any of the other m68k MMU's. So we need to create a set of definitions and support routines for the kernels paging functions. This is largely taken from Freescales BSP code for this (though it was a 2.6.25 kernel). I have cleaned it up alot from the original. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Matt Waddel <mwaddel@yahoo.com> Acked-by: Kurt Mahan <kmahan@xmission.com>
| * | | m68k: set register a2 to current if MMU enabled on ColdFireGreg Ungerer2011-12-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Virtual memory m68k systems build with register a2 dedicated to being the current proc pointer (non-MMU don't do this). Add code to the ColdFire interrupt and exception processing to set this on entry, and at context switch time. We use the same GET_CURRENT() macro that MMU enabled code uses - modifying it so that the assembler is ColdFire clean. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Matt Waddel <mwaddel@yahoo.com> Acked-by: Kurt Mahan <kmahan@xmission.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
| * | | m68k: add ColdFire 54xx CPU MMU memory init codeGreg Ungerer2011-12-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add code to the 54xx ColdFire CPU init to setup memory ready for the m68k paged memory start up. Some of the RAM variables that were specific to the non-mmu code paths now need to be used during this setup, so when CONFIG_MMU is enabled. Move these out of page_no.h and into page.h. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Matt Waddel <mwaddel@yahoo.com> Acked-by: Kurt Mahan <kmahan@xmission.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
| * | | m68k: use addr_limit checking for m68k CPUs that do no support address spacesGreg Ungerer2011-12-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ColdFire CPU family, and the original 68000, do not support separate address spaces like the other 680x0 CPU types. Modify the set_fs()/get_fs() functions and macros to use a thread_info addr_limit for address space checking. This is pretty much what all other architectures that do not support separate setable address spaces do. Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Matt Waddel <mwaddel@yahoo.com> Acked-by: Kurt Mahan <kmahan@xmission.com>
| * | | m68k: modify user space access functions to support ColdFire CPUsGreg Ungerer2011-12-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify the user space access functions to support the ColdFire V4e cores running with MMU enabled. The ColdFire processors do not support the "moves" instruction used by the traditional 680x0 processors for moving data into and out of another address space. They only support the notion of a single address space, and you use the usual "move" instruction to access that. Create a new config symbol (CONFIG_CPU_HAS_ADDRESS_SPACES) to mark the CPU types that support separate address spaces, and thus also support the sfc/dfc registers and the "moves" instruction that go along with that. The code is almost identical for user space access, so lets just use a define to choose either the "move" or "moves" in the assembler code. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Matt Waddel <mwaddel@yahoo.com> Acked-by: Kurt Mahan <kmahan@xmission.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
| * | | m68k: add TASK definitions for ColdFires running with MMUGreg Ungerer2011-12-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add appropriate TASK_SIZE and TASK_UNMAPPED_BASE definitions for running on ColdFire V4e cores with MMU enabled. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Matt Waddel <mwaddel@yahoo.com> Acked-by: Kurt Mahan <kmahan@xmission.com>
| * | | m68k: make interrupt definitions conditional on correct CPU typesGreg Ungerer2011-12-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The interrupt handling support defines and code is not so much conditional on an MMU being present (CONFIG_MMU), as it is on which type of CPU we are building for. So make the code conditional on the CPU types instead. The current irq.h is mostly specific to the interrupt code for the 680x0 CPUs, so it should only be used for them. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Matt Waddel <mwaddel@yahoo.com> Acked-by: Kurt Mahan <kmahan@xmission.com>
| * | | m68k: definitions for the ColdFire V4e MMU hardwareGreg Ungerer2011-12-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Basic register level definitions to support the internal MMU of the V4e ColdFire cores. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Matt Waddel <mwaddel@yahoo.com> Acked-by: Kurt Mahan <kmahan@xmission.com>
| * | | m68k: add machine and CPU definitions for ColdFire coresGreg Ungerer2011-12-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create machine and CPU definitions to support the ColdFire CPU family members that have a virtual memory management unit. The ColdFire V4e core contains an MMU, and it is quite different to any other 68k family members. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Matt Waddel <mwaddel@yahoo.com> Acked-by: Kurt Mahan <kmahan@xmission.com>
| * | | m68knommu: remove unused anchor.h include fileGreg Ungerer2011-12-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The code that used the anchor.h include file has long been removed from the kernel. Remove it too. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | | m68k: handle presence of 64bit mul/div instructions cleanlyGreg Ungerer2011-12-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The traditional 68000 processors and the newer reduced instruction set ColdFire processors do not support the 32*32->64 multiply or the 64/32->32 divide instructions. This is not a difference based on the presence of a hardware MMU or not. Create a new config symbol to mark that a CPU type doesn't support the longer multiply/divide instructions. Use this then as a basis for using the fast 64bit based divide (in div64.h) and for linking in the extra libgcc functions that may be required (mulsi3, divsi3, etc). Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
| * | | m68k: simpler m68k and ColdFire CPU's can use generic csum codeGreg Ungerer2011-12-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have two implementations of the IP checksuming code for the m68k arch. One uses the more advanced instructions available in 68020 and above processors, the other uses the simpler instructions available on the original 68000 processors and the modern ColdFire processors. This simpler code is pretty much the same as the generic lib implementation of the IP csum functions. So lets just switch over to using that. That means we can completely remove the checksum_no.c file, and only have the local fast code used for the more complex 68k CPU family members. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | | m68k: make fp register stores consistent for m68k and ColdFireGreg Ungerer2011-12-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no reason we can't make the saved fp registers the same for all m68k types and ColdFire. There is a little wasted space, but the code consistency and cleanliness is a big win. sigcontext.h is an exported header, but currently there is no in-mainline users of the !__uClinux__ and __mcoldfire__ case that this change effects. Even better this change actually makes this structure consistent with the out-of-mainline ColdFire/MMU code. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
| * | | m68k: print memory layout info in boot logGreg Ungerer2011-12-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Output a table of the kernel memory regions at boot time. This is taken directly from the ARM architecture code that does this. The table looks like this: Virtual kernel memory layout: vector : 0x00000000 - 0x00000400 ( 0 KiB) kmap : 0xd0000000 - 0xe0000000 ( 256 MiB) vmalloc : 0xc0000000 - 0xcfffffff ( 255 MiB) lowmem : 0x00000000 - 0x02000000 ( 32 MiB) .init : 0x00128000 - 0x00134000 ( 48 KiB) .text : 0x00020000 - 0x00118d54 ( 996 KiB) .data : 0x00118d60 - 0x00126000 ( 53 KiB) .bss : 0x00134000 - 0x001413e0 ( 53 KiB) This has been very useful while debugging the ColdFire virtual memory support code. But in general I think it is nice to know extacly where the kernel has layed everything out on boot. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | | m68k: remove thread_info struct from thread structGreg Ungerer2011-12-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently on m68k we have a comeplete thread_info structure stored inside of the thread_struct, and we also have it in the initial part of the kernel stack. Mostly the code currently uses the one inside of the thread_struct, only using the "task" pointer from the stack based one. This is wasteful and confusing, we should only have the single instance of thread_info inside the stack page. And this is the norm for all other architectures. This change makes m68k handle thread_info consistently on both MMU enabled and non-MMU setups. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | | m68k: remove duplicate asm offset for task thread.infoGreg Ungerer2011-12-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have a duplicate name and definition for the offset of the thread.info struct within the task struct in our asm-offsets.c code. Remove one of them, and consolidate to use a single define, TASK_INFO. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
| * | | m68k: Fall back to __gpio_to_irq() for non-arch GPIOsMark Brown2011-12-24
| |/ / | | | | | | | | | | | | | | | | | | | | | gpiolib provides __gpio_to_irq() to map gpiolib gpios to interrupts - hook that up on m68k. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* | | Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller2011-12-23
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: net/bluetooth/l2cap_core.c Just two overlapping changes, one added an initialization of a local variable, and another change added a new local variable. Signed-off-by: David S. Miller <davem@davemloft.net>
| * | m68k: Wire up process_vm_{read,write}vGeert Uytterhoeven2011-12-06
| |/ | | | | | | | | Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Greg Ungerer <gerg@uclinux.org>
* | Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller2011-11-21
|\| | | | | | | | | | | | | | | | | | | | | | | The forcedeth changes had a conflict with the conversion over to atomic u64 statistics in net-next. The libertas cfg.c code had a conflict with the bss reference counting fix by John Linville in net-next. Conflicts: drivers/net/ethernet/nvidia/forcedeth.c drivers/net/wireless/libertas/cfg.c
| * m68k/mac: Remove mac_irq_{en,dis}able() wrappersFinn Thain2011-11-08
| | | | | | | | | | Signed-off-by: Finn Thain <fthain@telegraphics.com.au> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
| * m68k/irq: Remove obsolete support for user vector interrupt fixupsGeert Uytterhoeven2011-11-08
| | | | | | | | | | | | It was used on Apollo only, before its conversion to genirq. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
| * m68k/irq: Remove obsolete m68k irq frameworkGeert Uytterhoeven2011-11-08
| | | | | | | | Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
| * m68k/q40: Convert Q40/Q60 to genirqGeert Uytterhoeven2011-11-08
| | | | | | | | | | | | | | | | q40_irq_handler() must be kept to translate ISA IRQs to the range 1-15. q40_probe_irq_o{ff,n}() become unused. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Richard Zidlicky <rz@linux-m68k.org>
| * m68k/irq: Add genirq supportGeert Uytterhoeven2011-11-08
| | | | | | | | | | | | | | Disabled on all platforms for now Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> [v1] Acked-by: Thomas Gleixner <tglx@linutronix.de>
| * m68k/irq: Rename {,__}m68k_handle_int()Geert Uytterhoeven2011-11-08
| | | | | | | | | | | | | | | | - Rename m68k_handle_int() to generic_handle_irq(), and drop the unneeded asmlinkage, - Rename __m68k_handle_int() to do_IRQ(). Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
| * m68k/irq: Add m68k_setup_irq_controller()Geert Uytterhoeven2011-11-08
| | | | | | | | | | | | | | This is a wrapper around m68k_setup_irq_chip() that discards its dummy second parameter, to ease the future transition to genirq. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
| * m68k/irq: Switch irq_chip methods to "struct irq_data *data"Geert Uytterhoeven2011-11-08
| | | | | | | | | | Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Thomas Gleixner <tglx@linutronix.de>
| * m68k/irq: Rename irq_node to irq_dataGeert Uytterhoeven2011-11-08
| | | | | | | | | | | | | | | | Make it more similar to the genirq version: - Add an irq field Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Thomas Gleixner <tglx@linutronix.de>
| * m68k/irq: Kill irq_node_t typedef, always use struct irq_nodeGeert Uytterhoeven2011-11-08
| | | | | | | | | | Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Thomas Gleixner <tglx@linutronix.de>
| * m68k/irq: Rename irq_controller to irq_chipGeert Uytterhoeven2011-11-08
| | | | | | | | | | | | | | | | | | | | Make it more similar to the genirq version: - Remove lock (unused as we don't do SMP anyway), - Prepend methods with irq_, - Make irq_startup() return unsigned int. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Thomas Gleixner <tglx@linutronix.de>
* | net: add wireless TX status socket optionJohannes Berg2011-11-09
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 802.1X EAPOL handshake hostapd does requires knowing whether the frame was ack'ed by the peer. Currently, we fudge this pretty badly by not even transmitting the frame as a normal data frame but injecting it with radiotap and getting the status out of radiotap monitor as well. This is rather complex, confuses users (mon.wlan0 presence) and doesn't work with all hardware. To get rid of that hack, introduce a real wifi TX status option for data frame transmissions. This works similar to the existing TX timestamping in that it reflects the SKB back to the socket's error queue with a SCM_WIFI_STATUS cmsg that has an int indicating ACK status (0/1). Since it is possible that at some point we will want to have TX timestamping and wifi status in a single errqueue SKB (there's little point in not doing that), redefine SO_EE_ORIGIN_TIMESTAMPING to SO_EE_ORIGIN_TXSTATUS which can collect more than just the timestamp; keep the old constant as an alias of course. Currently the internal APIs don't make that possible, but it wouldn't be hard to split them up in a way that makes it possible. Thanks to Neil Horman for helping me figure out the functions that add the control messages. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* m68knommu: create common externs for _ram* varsGreg Ungerer2011-10-18
| | | | | | | Create common extern definitions of _rambase, _ramstart and _ramend instead of them being externed when used in code. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: use generic section names in setup codeGreg Ungerer2011-10-18
| | | | | | | | We should be including and using sections.h to get at the extern definitions of the linker sections in the m68knommu startup code. Not defining them locally. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68k: merge the mmu and non-mmu traps.c filesGreg Ungerer2011-10-18
| | | | | | | | | | | | | The code for handling traps in the non-mmu case is a subset of the mmu enabled case. Merge the non-mmu traps_no.c code back to a single traps.c. There is actually no code mmu specific here at all, and the processor specific code (for the more complex 68020/68030/68040/68060) is already proplerly conditionaly used. The format of console exception dump is a little different, but I don't think will cause any one problems, it is purely for debug purposes. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68k: merge mmu and non-mmu include/asm/entry.h filesGreg Ungerer2011-10-18
| | | | | | | | | | | | | | | | | The changes in the mmu version of entry.h (entry_mm.h) and the non-mmu version (entry_no.h) are not about the presence or use of an MMU at all. The main changes are to support the ColdFire processors. The code for trap entry and exit for all types of 68k processor outside coldfire is the same. So merge the files back to a single entry.h and share the common 68k entry/exit code. Some changes are required for the non-mmu entry handlers to adopt the differing macros for system call and interrupt entry, but this is quite strait forward. The changes for the ColdFire remove a couple of instructions for the separate a7 register case, and are no worse for the older single a7 register case. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68knommu: fix problems with SPI/GPIO on ColdFire 520xPeter Turczak2011-10-18
| | | | | | | | | | | | | | | | | The problem has its root in the calculation of the set-port offsets (macro MCFGPIO_SETR() in arch/m68k/include/asm/gpio.h), this assumes that all ports have the same offset from the base port address (MCFGPIO_SETR) which is defined in mcf520xsim.h as an alias of MCFGIO_PSETR_BUSCTL. Because the BUSCTL and BE port do not have a set-register (see MCF5208 Reference Manual Page 13-10, Table 13-3) the offset calculations went wrong. Because the BE and BUSCTL port do not seem useful in these parts, as they lack a set register, I removed them and adapted the gpio chip bases which are also used for the offset-calculations. Now both setting and resetting the chip selects works as expected from userland and from the kernelspace. Signed-off-by: Peter Turczak <peter@turczak.de> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* m68k: fix __page_to_pfn for a const struct page argumentIan Campbell2011-08-23
| | | | | | | | | | | Fixes fallout due to the removal of the cast in commit aa462abe8aaf ("mm: fix __page_to_pfn for a const struct page argument") Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Cc: Andrew Morton <akpm@linux-foundation.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Cc: linux-m68k@lists.linux-m68k.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'for-linus' of ↵Linus Torvalds2011-07-31
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k: m68k/math-emu: Remove unnecessary code m68k/math-emu: Remove commented out old code m68k: Kill warning in setup_arch() when compiling for Sun3 m68k/atari: Prefix GPIO_{IN,OUT} with CODEC_ sparc: iounmap() and *_free_coherent() - Use lookup_resource() m68k/atari: Reserve some ST-RAM early on for device buffer use m68k/amiga: Chip RAM - Use lookup_resource() resources: Add lookup_resource() sparc: _sparc_find_resource() should check for exact matches m68k/amiga: Chip RAM - Offset resource end by CHIP_PHYSADDR m68k/amiga: Chip RAM - Use resource_size() to fix off-by-one error m68k/amiga: Chip RAM - Change chipavail to an atomic_t m68k/amiga: Chip RAM - Always allocate from the start of memory m68k/amiga: Chip RAM - Convert from printk() to pr_*() m68k/amiga: Chip RAM - Use tabs for indentation
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