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* [IA64-SGI] convert AMO address found in XPC's reserved pageDean Nelson2005-05-03
| | | | | | | | | | This patch detects the existence of an uncached physical AMO address setup by EFI's XPBOOT (SGI) and converts it to an uncached virtual AMO address. Depends on a patch submitted on 23 March 2005 with the subject of: [PATCH 2/3] SGI Altix cross partition functionality (2nd revision) Signed-off-by: Dean Nelson <dcn@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64-SGI] SGI Altix cross partition functionality [3/3]Dean Nelson2005-05-03
| | | | | | | | This patch contains the cross partition pseudo-ethernet driver (XPNET) functional support module. Signed-off-by: Dean Nelson <dcn@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64-SGI] SGI Altix cross partition functionality [2/3]Dean Nelson2005-05-03
| | | | | | | | This patch contains the communication module (XPC) for cross partition communication on a partitioned SGI Altix. Signed-off-by: Dean Nelson <dcn@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] manually apply changes to arch/ia64/sn/kernel/MakefileTony Luck2005-05-03
| | | | | | | cg-patch couldn't apply the patch to Makefile, and my dumb script rushed on and ran cg-commit without this change. Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64-SGI] SGI Altix cross partition functionality (2ndDean Nelson2005-05-03
| | | | | | | | This patch contains the shim module (XP) which interfaces between the communication module (XPC) and the functional support modules (like XPNET). Signed-off-by: Dean Nelson <dcn@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [PATCH] move cnodeid_to_nasid_table out of pdaDean Nelson2005-05-03
| | | | | | | | | | Another step in the effort to eliminate the SN pda structure. This patch moves the cnodeid_to_nasid_table field out of the pda, making it a standalone per-cpu data item, and exports it so it can be accessed by kernel modules. Signed-off-by: Dean Nelson <dcn@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64-SGI] Altix patch to add bricktype knowledge to tiocxBruce Losure2005-05-03
| | | | | | | | Here is a patch to enable the SGI tiocx bus driver to distingush between FPGA-attached h/w and non-FPGA-attached h/w. Signed-off-by: Bruce Losure <blosure@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64-SGI] Altix only: Remove hubdev SAL call Bruce Losure2005-05-03
| | | | | | | | | | | Hi Tony, This patch against ia64-test-2.6.12 fixes a bug where the tiocx code was inadvertently un-doing some address modifications done in earlier fixup code. This patch just removes the offending code. Signed-off-by: Bruce Losure <blosure@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] use fc.i for fluch_icache_range()David Mosberger-Tang2005-05-03
| | | | | | | | | | | | This is a small patch to switch fluch_icache_range() to use fc.i instead of fc. This would save time on processors which can establish i-cache coherency without flushing the cache-line out to memory (not that any current processors do). On existing processors, fc.i behaves like fc. The only caveat is that very old assemblers may not know about fc.i yet. Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] fix typos caught by new assemblerDavid Mosberger-Tang2005-05-03
| | | | | | | | | | | | Patch below fixes 3 trivial typos which are caught by the new assembler (v2.169.90). Please apply. [Note: fix to memcpy that was also part of this patch was separately applied from patches by H.J. and Andreas ... so the delta here only has the other two fixes. -Tony] Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] Fix memcpy_mck.S for current binutilsAndreas Schwab2005-05-03
| | | | | | | | The current ia64 assembler complains about mismatching .proc/.endp pairs. (Same patch also sent by H.J. Lu) Signed-off-by: Andreas Schwab <schwab@suse.de> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] Add config SCHED_SMTSuresh Siddha2005-05-03
| | | | | | | | | | | | | | Now that we have MC/MT detection patches in, appended patch allows us to configure MT scheduler optimizations. For now, we will this option off by default. There is some discussion going on lkml about setting up sched-domains which are absolutely needed (like for example, we shouldn't setup SMT domain for non MT processors). Once that patch goes in, we can enable this option by default. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [PATCH] convert that currently tests _NSIG directly to use valid_signal()Jesper Juhl2005-05-01
| | | | | | | | | Convert most of the current code that uses _NSIG directly to instead use valid_signal(). This avoids gcc -W warnings and off-by-one errors. Signed-off-by: Jesper Juhl <juhl-lkml@dif.dk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] consolidate sys_shmatStephen Rothwell2005-05-01
| | | | | | Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* From: jbarnes@sgi.comJesse Barnes2005-04-25
| | | | | | | | | | | | | | | | | [IA64] fix ia64 Kconfig to allow CONFIG_PM on sn2 This probably should have been fixed when I fixed up the generic build for discontig+numa machines, but oh well. CONFIG_PM is allowable for generic builds but not for sn2 builds, which doesn't make much sense, and in fact breaks the build if recent ACPI bits are added to the tree. It looks like the only arch that needs to prevent CONFIG_PM stuff is the ski simulator (though those options could probably use some cleanup as well), so remove the big conditional and replace it with a simple test for IA64_HP_SIM instead. Signed-off-by: Jesse Barnes <jbarnes@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] iosapic.c: typo ... s/spin_unlock_irq/spin_unlock/Kenji Kaneshige2005-04-25
| | | | | | | vector sharing patch had a typo ... mismatched spin_lock() with a spin_unlock_irq(). Fix from Kenji Kaneshige. Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] print "siblings" before {physical,core,thread} idTony Luck2005-04-25
| | | | | | | | Rohit and Suresh changed their mind about the order to print things in /proc/cpuinfo, but didn't include the change in the version of the patch they sent to me. Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] vector sharing (Large I/O system support)Kenji Kaneshige2005-04-25
| | | | | | | | | | | | | | | Current ia64 linux cannot handle greater than 184 interrupt sources because of the lack of vectors. The following patch enables ia64 linux to handle greater than 184 interrupt sources by allowing the same vector number to be shared by multiple IOSAPIC's RTEs. The design of this patch is besed on "Intel(R) Itanium(R) Processor Family Interrupt Architecture Guide". Even if you don't have a large I/O system, you can see the behavior of vector sharing by changing IOSAPIC_LAST_DEVICE_VECTOR to fewer value. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] multi-core/multi-thread identificationSuresh Siddha2005-04-25
| | | | | | | | | | | | | | | | | | | | | | Version 3 - rediffed to apply on top of Ashok's hotplug cpu patch. /proc/cpuinfo output in step with x86. This is an updated MC/MT identification patch based on the previous discussions on list. Add the Multi-core and Multi-threading detection for IPF. - Add new core and threading related fields in /proc/cpuinfo. Physical id Core id Thread id Siblings - setup the cpu_core_map and cpu_sibling_map appropriately - Handles Hot plug CPU Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Gordon Jin <gordon.jin@intel.com> Signed-off-by: Rohit Seth <rohit.seth@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] __copy_user breaks on unaligned srcKeith Owens2005-04-25
| | | | | | | | | | | memcpy_mck.S::__copy_user breaks in the prefetch code under these conditions :- * src is unaligned and * dst is near the end of a page and * the page after dst is unmapped. Signed-off-by: Keith Owens <kaos@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] Need to handle lfetch in "no_context" case.Tony Luck2005-04-25
| | | | | | | Thanks to Mark for tracking down this one. Users of __copy_from_user_inatomic() will be sad if we don't handle lfetch faults for the "no_context" case. Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64-SGI] Altix SN add support for slots in geoid_t locatorMark Goodwin2005-04-25
| | | | | | | | | | | This patch against ia64-test-2.6.12 is needed for forthcoming Altix chipsets. It renames geoid_any_t to geoid_common_t and splits the 8bit 'slab' field into two 4bit fields for 'slab' and 'slot'. Similar changes in the Altix SAL will retain backward compatibility for old kernels. Signed-off-by: Mark Goodwin <markgw@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] fix syscall-optimization goofDavid Mosberger-Tang2005-04-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | Sadly, I goofed in this syscall-tuning patch: ChangeSet 1.1966.1.40 2005/01/22 13:31:05 davidm@hpl.hp.com [IA64] Improve ia64_leave_syscall() for McKinley-type cores. Optimize ia64_leave_syscall() a bit better for McKinley-type cores. The patch looks big, but that's mostly due to renaming r16/r17 to r2/r3. Good for a 13 cycle improvement. The problem is that the size of the physical stacked registers was loaded into the wrong register (r3 instead of r17). Since r17 by coincidence always had the value 1, this had the effect of turning rse_clear_invalid into a no-op. That poses the risk of leaking kernel state back to user-land and is hence not acceptable. The fix below is simple, but unfortunately it costs us about 28 cycles in syscall overhead. ;-( Unfortunately, there isn't much we can do about that since those registers have to be cleared one way or another. --david Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64-SGI] Shub2 BTE support - BTE recovery codeRuss Anderson2005-04-25
| | | | | | | | | | patch 2: Shub2 BTE recovery code will be implemented in SAL. Define the SAL interface. Modify bte_error to call SAL for shub2. Signed-off-by: Russ Anderson <rja@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64-SGI] Add new MMR definitions/Modify BTE initialiation&copy.Russ Anderson2005-04-25
| | | | | | | | | | patch 1: Add new MMR definitions. Modify BTE initialiation. Modify BTE copy. Signed-off-by: Russ Anderson <rja@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64-SGI] disable TIOCA GART TLB prefetchingMark Maule2005-04-25
| | | | | | | Patch to disable SGI TIOCA GART TLB prefetching due to hw bug. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] MAX_PGT_FREES_PER_PASS must be 'L' to avoid warningTony Luck2005-04-25
| | | | | | 'min' is very picky about types of arguments, make it happy Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] sba_iommu bug fixesAlex Williamson2005-04-25
| | | | | | | | | | | | | | | | | | | This fixes a couple of bugs in the zx1/sx1000 sba_iommu. These are all pretty low likelihood of hitting. The first problem is a simple off by one, deep in the sba_alloc_range() error path. Surrounding that was a lock ordering problem that could have potentially deadlocked with the order the locks are grabbed in sba_unmap_single(). I moved the resource locking into sba_search_bitmap() to prevent this. Finally, there's a potential race between unmapping pdir entries and marking incoming DMA pages clean. If you see any oddities, please let me know, but I've tested it pretty thoroughly here. Tony, please apply. Thanks, BTW, many of the options in this driver not on by default are becoming more and more broken. I'll be working on some patches to clean them out, but I wanted to get this bug fix out first. Signed-off-by: Alex Williamson <alex.williamson@hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] Percpu quicklist for combined allocator for pgd/pmd/pte.Robin Holt2005-04-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces using the quicklists for pgd, pmd, and pte levels by combining the alloc and free functions into a common set of routines. This greatly simplifies the reading of this header file. This patch is simple but necessary for large numa configurations. It simply ensures that only pages from the local node are added to a cpus quicklist. This prevents the trapping of pages on a remote nodes quicklist by starting a process, touching a large number of pages to fill pmd and pte entries, migrating to another node, and then unmapping or exiting. With those conditions, the pages get trapped and if the machine has more than 100 nodes of the same size, the calculation of the pgtable high water mark will be larger than any single node so page table cache flushing will never occur. I ran lmbench lat_proc fork and lat_proc exec on a zx1 with and without this patch and did not notice any change. On an sn2 machine, there was a slight improvement which is possibly due to pages from other nodes trapped on the test node before starting the run. I did not investigate further. This patch shrinks the quicklist based upon free memory on the node instead of the high/low water marks. I have written it to enable preemption periodically and recalculate the amount to shrink every time we have freed enough pages that the quicklist size should have grown. I rescan the nodes zones each pass because other processess may be draining node memory at the same time as we are adding. Signed-off-by: Robin Holt <holt@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64-SGI]Bruce Losure2005-04-25
| | | | | | | Missed the "bk new" for this file in the last commit. Signed-off-by: Bruce Losure <blosure@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64-SGI] Altix: enable poweroffAaron J Young2005-04-25
| | | | | | | | | | | | | | | | | This patch adds the necessary "hook" to allow SGI/SN machines to perform a system power off upon a 'init 0', 'halt -p', 'poweroff' or 'shutdown -h'. The "hook" is to set the pm_power_off callback to ia64_sn_power_down(). pm_power_off is checked in machine_power_off()/do_poweroff() and, if set, is executed. ia64_sn_power_down() is a function already present (but not used currently) in the sn kernel. ia64_sn_power_down() makes a SAL call to execute the power off. Signed-off-by: Aaron J Young <ayoung@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64-SGI] Bus driver for the CX port of SGI's TIO chip.Bruce Losure2005-04-25
| | | | | | | | This patch is to provide CX port infrastructure for SGI TIO-based h/w. Also a 'core services' driver for SGI FPGA-based h/w. Signed-off-by: Bruce Losure <blosure@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] perfmon: make pfm_sysctl a global, and other cleanupStephane Eranian2005-04-25
| | | | | | | | | | | | | | | | | | - make pfm_sysctl a global such that it is possible to enable/disable debug printk in sampling formats using PFM_DEBUG. - remove unused pfm_debug_var variable - fix a bug in pfm_handle_work where an BUG_ON() could be triggered. There is a path where pfm_handle_work() can be called with interrupts enabled, i.e., when TIF_NEED_RESCHED is set. The fix correct the masking and unmasking of interrupts in pfm_handle_work() such that we restore the interrupt mask as it was upon entry. signed-off-by: stephane eranian <eranian@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64-SGI] Shub2 provides an addition of 2 External Interrupt events.Colin Ngam2005-04-25
| | | | | Signed-off-by: Colin Ngam <cngam@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64-SGI] Altix SN topology fix potential infinite loopMark Goodwin2005-04-25
| | | | | | | Fix infinite loop if sn_hwperf_location_to_bpos() fails. Signed-off-by: Mark Goodwin <markgw@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64-SGI] Altix SN topology support for new chipsets and pci topologyMark Goodwin2005-04-25
| | | | | | | | | | | please accept this patch to the Altix SN platform topology export interface to support new chipsets and to export PCI topology. This follows on top of Jack Steiner's patch dated March 1st ("New chipset support for SN platform"). Signed-off-by: Mark Goodwin <markgw@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] speed up syscall path a bit moreDavid Mosberger-Tang2005-04-25
| | | | | | | | | | Recently I noticed that clearing ar.ssd/ar.csd right before srlz.d is causing significant stalling in the syscall path. The patch below fixes that by moving the register-writes after srlz.d. On a Madison, this drops break-based getpid() from 241 to 226 cycles (-15 cycles). Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] Tighten up unw_unwind_to_user checkKeith Owens2005-04-25
| | | | | | | | | | | | | | Detect user space by the unwind frame with predicate PRED_USER_STACK set, instead of a user space IP. Tighten up the last ditch check for running off the top of the kernel stack. Based on a suggestion by David Mosberger, reworked to fit the current tree. This survives my stress test which used to break 2.6.9 kernels. Unlike 2.6.11, the stress test now unwinds to the correct point, so gdb can get the user space registers. Signed-off-by: Keith Owens <kaos@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] add missing cpu_relax() in ITC syncing codeDavid Mosberger-Tang2005-04-25
| | | | | | | Call cpu_relax() in busy-waiting loops of the ITC-syncing code. Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64-SGI] altix: tioca chip driver (agp)Mark Maule2005-04-25
| | | | | | | | Provide a driver for the altix TIOCA AGP chipset. An agpgart backend will be provided as a separate patch. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64-SGI] sn2-move-pci-headers.patchMark Maule2005-04-25
| | | | | | | | Move a couple of headers out of arch/ia64/sn/include/pci and into include/asm-ia64/sn. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64-SGI] sn2-pci-dma-abstraction.patchMark Maule2005-04-25
| | | | | | | | Provide an abstraction of the altix pci dma runtime layer so that multiple pci-based bridges can be supported. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] Fix build errors for !HOTPLUG case.Ashok Raj2005-04-22
| | | | | Signed-off-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] cpu hotplug: return offlined cpus to SALAshok Raj2005-04-22
| | | | | | | | | | | | | | | | This patch is required to support cpu removal for IPF systems. Existing code just fakes the real offline by keeping it run the idle thread, and polling for the bit to re-appear in the cpu_state to get out of the idle loop. For the cpu-offline to work correctly, we need to pass control of this CPU back to SAL so it can continue in the boot-rendez mode. This gives the SAL control to not pick this cpu as the monarch processor for global MCA events, and addition does not wait for this cpu to checkin with SAL for global MCA events as well. The handoff is implemented as documented in SAL specification section 3.2.5.1 "OS_BOOT_RENDEZ to SAL return State" Signed-off-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [IA64] ia32_signal.c: erroneous use of memset/memcpyArun Sharma2005-04-22
| | | | | | | | | | | | | Found by Alexander Nyberg, improved by Bjorn Helgaas. - Fix the incorrect argument to sizeof() - looks like memcpy() code pass was dervived from code that used copy_from_user(). But in this case we are doing to kernel space to kernel space copy, so memcpy is the right routine, but it doesn't return an error code. Signed-off-by: Arun Sharma <arun.sharma@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
* [PATCH] freepgt: hugetlb_free_pgd_rangeHugh Dickins2005-04-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ia64 and ppc64 had hugetlb_free_pgtables functions which were no longer being called, and it wasn't obvious what to do about them. The ppc64 case turns out to be easy: the associated tables are noted elsewhere and freed later, safe to either skip its hugetlb areas or go through the motions of freeing nothing. Since ia64 does need a special case, restore to ppc64 the special case of skipping them. The ia64 hugetlb case has been broken since pgd_addr_end went in, though it probably appeared to work okay if you just had one such area; in fact it's been broken much longer if you consider a long munmap spanning from another region into the hugetlb region. In the ia64 hugetlb region, more virtual address bits are available than in the other regions, yet the page tables are structured the same way: the page at the bottom is larger. Here we need to scale down each addr before passing it to the standard free_pgd_range. Was about to write a hugely_scaled_down macro, but found htlbpage_to_page already exists for just this purpose. Fixed off-by-one in ia64 is_hugepage_only_range. Uninline free_pgd_range to make it available to ia64. Make sure the vma-gathering loop in free_pgtables cannot join a hugepage_only_range to any other (safe to join huges? probably but don't bother). Signed-off-by: Hugh Dickins <hugh@veritas.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] freepgt: free_pgtables use vma listHugh Dickins2005-04-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recent woes with some arches needing their own pgd_addr_end macro; and 4-level clear_page_range regression since 2.6.10's clear_page_tables; and its long-standing well-known inefficiency in searching throughout the higher-level page tables for those few entries to clear and free: all can be blamed on ignoring the list of vmas when we free page tables. Replace exit_mmap's clear_page_range of the total user address space by free_pgtables operating on the mm's vma list; unmap_region use it in the same way, giving floor and ceiling beyond which it may not free tables. This brings lmbench fork/exec/sh numbers back to 2.6.10 (unless preempt is enabled, in which case latency fixes spoil unmap_vmas throughput). Beware: the do_mmap_pgoff driver failure case must now use unmap_region instead of zap_page_range, since a page table might have been allocated, and can only be freed while it is touched by some vma. Move free_pgtables from mmap.c to memory.c, where its lower levels are adapted from the clear_page_range levels. (Most of free_pgtables' old code was actually for a non-existent case, prev not properly set up, dating from before hch gave us split_vma.) Pass mmu_gather** in the public interfaces, since we might want to add latency lockdrops later; but no attempt to do so yet, going by vma should itself reduce latency. But what if is_hugepage_only_range? Those ia64 and ppc64 cases need careful examination: put that off until a later patch of the series. What of x86_64's 32bit vdso page __map_syscall32 maps outside any vma? And the range to sparc64's flush_tlb_pgtables? It's less clear to me now that we need to do more than is done here - every PMD_SIZE ever occupied will be flushed, do we really have to flush every PGDIR_SIZE ever partially occupied? A shame to complicate it unnecessarily. Special thanks to David Miller for time spent repairing my ceilings. Signed-off-by: Hugh Dickins <hugh@veritas.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-16
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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