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* [Blackfin] arch: use common flash driver to setup partitions rather than the ...Mike Frysinger2008-01-24
* [Blackfin] arch: enable generic GPIO based I2C driver in STAMP-BF533, EZKIT-B...Bryan Wu2008-01-24
* [Blackfin] arch: fix bug when DMA operation related core B of BF561Enrik Berkhan2007-12-24
* [Blackfin] arch: replace current blackfin specific pfbutton driver with kerne...Michael Hennerich2008-01-27
* [Blackfin] arch: add Hitachi TX09D70VM1CDA TFT LCD driver resource to Blackfi...Michael Hennerich2008-01-27
* Blackfin arch: add AXIS AX88180 Gigabit Ethernet Hardware and Driver to board...Michael Hennerich2007-11-17
* Blackfin arch: relocate linux/usb_isp1362.h to linux/usb/isp1362.h like in ne...Mike Frysinger2007-11-15
* Blackfin arch: remove useless CONFIG_IRQCHIP_DEMUX_GPIOMike Frysinger2007-11-15
* Blackfin arch: split board selection off into mach subdirsMike Frysinger2007-11-15
* Blackfin arch: move hard coded pin_req to board fileBryan Wu2007-11-12
* Blackfin arch: use "char bfin_board_name[]" rather than "char *bfin_board_nam...Mike Frysinger2007-10-21
* Blackfin arch: Print out debug info, as early as possibleRobin Getz2007-10-09
* Blackfin arch: rewrite our reboot code in CMike Frysinger2007-10-10
* Blackfin arch: allow people to select the feature that is unavailable to the ...Mike Frysinger2007-08-05
* Blackfin arch: Add ability to expend the hardware trace bufferRobin Getz2007-07-24
* Blackfin arch: Fix CCLK and SCLK checksRobin Getz2007-08-03
* Blackfin arch: use HI/LO macros rather than masking the bit ranges ourselvesMike Frysinger2007-07-24
* Blackfin arch: revise anomaly handling by basing things on the compiler not t...Mike Frysinger2007-07-24
* Blackfin arch: update platform driver resource information to all board filesBryan Wu2007-10-10
* Blackfin arch: setup aliases for some core Core A MMRsMike Frysinger2007-07-24
* Blackfin arch: cleanup warnings from checkpatch -- no functional changesMike Frysinger2007-07-12
* Blackfin arch: Clean up trace buffer handling, No major functional changes.Robin Getz2007-06-21
* Blackfin arch: initial supporting for BF548-EZKITRoy Huang2007-07-12
* Blackfin arch: move more of our startup code to .init so it can be freed once...Mike Frysinger2007-06-11
* Blackfin arch: unify differences between our diff head.S files -- no function...Mike Frysinger2007-06-11
* Blackfin arch: spelling fixesSimon Arlott2007-06-11
* Blackfin arch: dont clear the bit that tells coreb to start bootingMike Frysinger2007-05-21
* Blackfin arch: document why we have to touch the UART peripheral in our boot ...Mike Frysinger2007-05-21
* Blackfin arch: issue reset via SWRST so we dont clobber the watchdog stateMike Frysinger2007-05-21
* Blackfin arch: move board specific setup out of common init code and into the...Mike Frysinger2007-05-21
* Blackfin arch: dont clear status register bits in SWRST so we can actually us...Mike Frysinger2007-05-21
* Blackfin arch: initial tepla-bf561 board supportMike Frysinger2007-05-21
* Blackfin arch: Add configuration data for ISP176x on BF561Michael Hennerich2007-05-21
* blackfin architectureBryan Wu2007-05-07
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 15:28:54 -0500
class="hl opt">: /* No outputs */ : "r" (tag), "r" (addr), "i" (ASI_IC_TAG)); } static __inline__ unsigned long spitfire_get_dtlb_data(int entry) { unsigned long data; __asm__ __volatile__("ldxa [%1] %2, %0" : "=r" (data) : "r" (entry << 3), "i" (ASI_DTLB_DATA_ACCESS)); /* Clear TTE diag bits. */ data &= ~0x0003fe0000000000UL; return data; } static __inline__ unsigned long spitfire_get_dtlb_tag(int entry) { unsigned long tag; __asm__ __volatile__("ldxa [%1] %2, %0" : "=r" (tag) : "r" (entry << 3), "i" (ASI_DTLB_TAG_READ)); return tag; } static __inline__ void spitfire_put_dtlb_data(int entry, unsigned long data) { __asm__ __volatile__("stxa %0, [%1] %2\n\t" "membar #Sync" : /* No outputs */ : "r" (data), "r" (entry << 3), "i" (ASI_DTLB_DATA_ACCESS)); } static __inline__ unsigned long spitfire_get_itlb_data(int entry) { unsigned long data; __asm__ __volatile__("ldxa [%1] %2, %0" : "=r" (data) : "r" (entry << 3), "i" (ASI_ITLB_DATA_ACCESS)); /* Clear TTE diag bits. */ data &= ~0x0003fe0000000000UL; return data; } static __inline__ unsigned long spitfire_get_itlb_tag(int entry) { unsigned long tag; __asm__ __volatile__("ldxa [%1] %2, %0" : "=r" (tag) : "r" (entry << 3), "i" (ASI_ITLB_TAG_READ)); return tag; } static __inline__ void spitfire_put_itlb_data(int entry, unsigned long data) { __asm__ __volatile__("stxa %0, [%1] %2\n\t" "membar #Sync" : /* No outputs */ : "r" (data), "r" (entry << 3), "i" (ASI_ITLB_DATA_ACCESS)); } static __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page) { __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" "membar #Sync" : /* No outputs */ : "r" (page | 0x20), "i" (ASI_DMMU_DEMAP)); } static __inline__ void spitfire_flush_itlb_nucleus_page(unsigned long page) { __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" "membar #Sync" : /* No outputs */ : "r" (page | 0x20), "i" (ASI_IMMU_DEMAP)); } /* Cheetah has "all non-locked" tlb flushes. */ static __inline__ void cheetah_flush_dtlb_all(void) { __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" "membar #Sync" : /* No outputs */ : "r" (0x80), "i" (ASI_DMMU_DEMAP)); } static __inline__ void cheetah_flush_itlb_all(void) { __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" "membar #Sync" : /* No outputs */ : "r" (0x80), "i" (ASI_IMMU_DEMAP)); } /* Cheetah has a 4-tlb layout so direct access is a bit different. * The first two TLBs are fully assosciative, hold 16 entries, and are * used only for locked and >8K sized translations. One exists for * data accesses and one for instruction accesses. * * The third TLB is for data accesses to 8K non-locked translations, is * 2 way assosciative, and holds 512 entries. The fourth TLB is for * instruction accesses to 8K non-locked translations, is 2 way * assosciative, and holds 128 entries. * * Cheetah has some bug where bogus data can be returned from * ASI_{D,I}TLB_DATA_ACCESS loads, doing the load twice fixes * the problem for me. -DaveM */ static __inline__ unsigned long cheetah_get_ldtlb_data(int entry) { unsigned long data; __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t" "ldxa [%1] %2, %0" : "=r" (data) : "r" ((0 << 16) | (entry << 3)), "i" (ASI_DTLB_DATA_ACCESS)); return data; } static __inline__ unsigned long cheetah_get_litlb_data(int entry) { unsigned long data; __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t" "ldxa [%1] %2, %0" : "=r" (data) : "r" ((0 << 16) | (entry << 3)), "i" (ASI_ITLB_DATA_ACCESS)); return data; } static __inline__ unsigned long cheetah_get_ldtlb_tag(int entry) { unsigned long tag; __asm__ __volatile__("ldxa [%1] %2, %0" : "=r" (tag) : "r" ((0 << 16) | (entry << 3)), "i" (ASI_DTLB_TAG_READ)); return tag; } static __inline__ unsigned long cheetah_get_litlb_tag(int entry) { unsigned long tag; __asm__ __volatile__("ldxa [%1] %2, %0" : "=r" (tag) : "r" ((0 << 16) | (entry << 3)), "i" (ASI_ITLB_TAG_READ)); return tag; } static __inline__ void cheetah_put_ldtlb_data(int entry, unsigned long data) { __asm__ __volatile__("stxa %0, [%1] %2\n\t" "membar #Sync" : /* No outputs */ : "r" (data), "r" ((0 << 16) | (entry << 3)), "i" (ASI_DTLB_DATA_ACCESS)); } static __inline__ void cheetah_put_litlb_data(int entry, unsigned long data) { __asm__ __volatile__("stxa %0, [%1] %2\n\t" "membar #Sync" : /* No outputs */ : "r" (data), "r" ((0 << 16) | (entry << 3)), "i" (ASI_ITLB_DATA_ACCESS)); } static __inline__ unsigned long cheetah_get_dtlb_data(int entry, int tlb) { unsigned long data; __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t" "ldxa [%1] %2, %0" : "=r" (data) : "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_DATA_ACCESS)); return data; } static __inline__ unsigned long cheetah_get_dtlb_tag(int entry, int tlb) { unsigned long tag; __asm__ __volatile__("ldxa [%1] %2, %0" : "=r" (tag) : "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_TAG_READ)); return tag; } static __inline__ void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb) { __asm__ __volatile__("stxa %0, [%1] %2\n\t" "membar #Sync" : /* No outputs */ : "r" (data), "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_DATA_ACCESS)); } static __inline__ unsigned long cheetah_get_itlb_data(int entry) { unsigned long data; __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t" "ldxa [%1] %2, %0" : "=r" (data) : "r" ((2 << 16) | (entry << 3)), "i" (ASI_ITLB_DATA_ACCESS)); return data; } static __inline__ unsigned long cheetah_get_itlb_tag(int entry) { unsigned long tag; __asm__ __volatile__("ldxa [%1] %2, %0" : "=r" (tag) : "r" ((2 << 16) | (entry << 3)), "i" (ASI_ITLB_TAG_READ)); return tag; } static __inline__ void cheetah_put_itlb_data(int entry, unsigned long data) { __asm__ __volatile__("stxa %0, [%1] %2\n\t" "membar #Sync" : /* No outputs */ : "r" (data), "r" ((2 << 16) | (entry << 3)), "i" (ASI_ITLB_DATA_ACCESS)); } #endif /* !(__ASSEMBLY__) */ #endif /* !(_SPARC64_SPITFIRE_H) */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 15:28:54 -0500