| Commit message (Collapse) | Author | Age |
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Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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Patch adds DT entries for clockgen A9
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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Patch adds DT entries for clockgen D0/D2/D3
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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Patch adds DT entries for clockgen C0
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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Patch adds DT entries for clockgen A0
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Olivier Bideau <olivier.bideau@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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ARM: DT: STi: STiH416: Add DT node for ST's SATA device
Cc: devicetree@vger.kernel.org
Acked-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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The MiPHY365x is a Generic PHY which can serve various SATA or PCIe
devices. It has 2 ports which it can use for either; both SATA, both
PCIe or one of each in any configuration.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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We supply two of these. The first is controlled by the System Configuration
registers and the second one provided is a more traditional 'memory mapped'
variant. Each are handled by they own sub-driver.
Signed-off-by: Ajit Pal Singh <ajitpal.singh@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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The second controller is only present on the stih416 SoC. Also
mark this as non-removeable as its eMMC.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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Because the first sdhci controller is present on both stih415 and
stih416 SoC which can both populate the b2020 board, it can be
enabled in the generic DT file.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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This patch adds device tree config for the sdhci controller
on the stih415 SoC.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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This patch adds the required pin config for the sdhci controller
present in the stih415 SoC.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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This patch adds device tree config for both sdhci controllers
on the stih416 SoC.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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This adds the required pin config for both SDHCI controllers on
the stih416 SoC.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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This patch adds the reset controller DT nodes for the powerdown,
softreset and picophy controllers.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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The STiH407 is a STMicroelectronics Digital Consumer electronics
family, targetted at set-top-box and other audio/video applications.
This patch selects the reset controller driver for this family which
is essential to take various IP's on the SoC out of powerdown / reset.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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Suggested-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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into next/dt
Merge "Broadcom Cygnus SoC Device Tree changes" from Florian Fianelli:
This patchset contains initial support for Broadcom's Cygnus SoC based on our
iProc architecture. Initial support is minimal and includes just the mach
platform code, clock driver, and a basic device tree configuration. Peripheral
drivers will be submitted soon, as will device tree configurations for other
Cygnus board variants.
These are the Device Tree changes
* tag 'arm-soc/for-3.18/cygnus-dts-v9' of http://github.com/brcm/linux:
ARM: dts: Enable Broadcom Cygnus SoC
dt-bindings: Document Broadcom Cygnus SoC and clocks
Signed-off-by: Olof Johansson <olof@lixom.net>
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DT files to enable cygnus consisting on reference designs
and cygnus core configuration.
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Merge "first bunch on Rockchip dt changes" from Heiko Stübner:
First hunk of rockchip devicetree patches, containing:
- cpu operating points and supplies
- dma support for spi controllers
- i2s on rk3066 and rk3188
- default core clock settings for rk3288
* tag 'v3.19-rockchip-dts1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: Add SPI DMA into rk3288.dtsi
ARM: dts: rockchip: enable init rate for clock
ARM: dts: rockchip: add I2S controllers for rk3066 and rk3188
ARM: dts: rockchip: enable DMA on SPI for rk3066 and rk3188
ARM: dts: rockchip: add cpu supplies to boards
ARM: dts: rockchip: add operating points and armclk references
Signed-off-by: Olof Johansson <olof@lixom.net>
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Now that SPI DMA has been fixed on rk3288 we can enable it.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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We need to initialize PLL rate and some of bus clock rate while
kernel init, for there is no other module will do that.
Basically on rk3288 we use GPLL for cpu bus, peripheral bus and
most of peripheral clock, CPLL for devices who require 50M/200M
clock rate, leave NPLL behind for special requirement from
display system.
The common-clock-framework will help us to select best source for
child clocks after we init the PLLs propriety.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add the I2S/PCM controller nodes and pin controls for rk3066 and rk3188.
Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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According to the RK3066 and RK3188 TRM, the two SPI controllers support DMA
handshake interface. Add the DMA properties so they can be used when needed.
Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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This adds the cpu-supplies to the curie2, radxarock and rk3288-evb-rk808 boards.
The rk3288-evb-act8846 variant cannot provide the cpu-regulator at the moment
so will get its supply later.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add basic OPP entries for current supported Rockchip SoCs.
The operating points are currently very conservative, so individual
boards may opt to redefine them.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Merge "Renesas ARM Based SoC r8a73a4 DT Timers Updates for v3.19" from Simon
Horman:
* Initialise CMT1 timer using DT
* tag 'renesas-r8a73a4-dt-timers-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a73a4: Remove empty r8a73a4_add_dt_devices
ARM: shmobile: ape6evm-reference: Initialise CMT1 device using DT
ARM: shmobile: r8a73a4: Rename cmt registration helper
ARM: shmobile: r8a73a4: Add CMT1 node
Signed-off-by: Olof Johansson <olof@lixom.net>
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r8a73a4_add_dt_devices() no longer enables any devices
so remove it.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Initialise CMT1 device using DT when booting ape6evm
using DT-reference.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Rename r8a7790_register_cmt() as r8a73a4_register_cmt() to
reflect name of the SoC in use. The use of r8a7790 appears
to be due to historical sharing of code from that SoC.
Shared code is no longer used.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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This describes all of the CMT1 hardware of the r8a73a4.
The node is disabled and may be enabled as necessary by board DTS files.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Merge "Renesas ARM Based SoC DT Cleanups for v3.19" from Simon Horman:
* Add chosen/stdout-path to DTS files for shmobile boards
* Remove r7s72100-genmai.dtb for ARCH_SHMOBILE_LEGACY
- The corresponding board file has already been removed
* Sort dts nodes by address
* Sort SHMOBILE dtbs alphabetically in Makefile
* tag 'renesas-dt-cleanups-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: kzm9d dts: Add chosen/stdout-path
ARM: shmobile: kzm9g-reference dts: Add chosen/stdout-path
ARM: shmobile: alt dts: Add chosen/stdout-path
ARM: shmobile: koelsch dts: Add chosen/stdout-path
ARM: shmobile: henninger dts: Add chosen/stdout-path
ARM: shmobile: lager dts: Add chosen/stdout-path
ARM: shmobile: marzen dts: Add chosen/stdout-path
ARM: shmobile: bockw-reference dts: Add chosen/stdout-path
ARM: shmobile: armadillo800eva dts: Add chosen/stdout-path
ARM: shmobile: ape6evm-reference dts: Add chosen/stdout-path
ARM: shmobile: genmai dts: Add chosen/stdout-path
ARM: shmobile: emev2 dtsi: Add uart* labels for easier referencing
ARM: shmobile: emev2 dtsi: Use generic names for device nodes
ARM: shmobile: r7s72100: Remove r7s72100-genmai.dtb for ARCH_SHMOBILE_LEGACY
ARM: shmobile: r8a73a4: sort dtsi file by address
ARM: shmobile: kzm9d: sort dts file by address
ARM: shmobile: r7s72100: sort dtsi file by address
ARM: shmobile: r8a73a4: Remove spurious dma-multiplexer base addresses
ARM: dts: Sort SHMOBILE dtbs alphabetically
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/dt
Merge "RealView DeviceTree support for v3.19" from Linus Walleij:
- Device Tree implementation for the ARM RealView boards
- DTS file for the ARM RealView PB1176
- Updates on top of the same DTS file
* tag 'arm-realview-dt-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: realview: add MMCI to the PB1176 DTS
ARM: realview: add KMIs to the PB1176 DTS
ARM: realview: add FPGA UART4 to PB1176 DTS
ARM: realview: add PL022 SSP/SPI block to PB1176 DTS
ARM: realview: add RTC clocks to device tree
ARM: realview: add charlcd to PB1176 device tree
ARM: realview: add PL061 GPIO to the PB1176 DTS
ARM: realview: move DT GIC to FPGA node
ARM: realview: add device tree and bindings for PB1176
ARM: realview: basic device tree implementation
Signed-off-by: Olof Johansson <olof@lixom.net>
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This adds the MMC/SD card reader (MMCI) block to the
RealView PB1176 DTS file. Add a special MCLK derived clock
and a fixed regulator to represent the 3.3V rail hardwired
to the MMC reader on the board.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This adds the Keyboard Mouse Interface (KMI) blocks to the
PB1176 DTS file, and defines the special KMI clock derived
from the 24 MHz chrystal.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This adds the UART4 found on the FPGA to the PB1176 DTS
file.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add the PL022 SSP/SPI block to the PL1176 DTS file, also
define the separate SSPCLK clock derived from the 24MHz
chrystal.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The PB1176 has two PL031 RTC clocks, one in the devchip and one
in the FPGA. Add them to the device tree.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Extend the PB1176 device tree with the character LCD device.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This adds the PL061 GPIO instances found on the PB1176 devchip
and the FPGA to the DTS file.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This creates a node in the device tree to hold the FPGA devices
as a "simple-bus" and moves the GIC found on the FPGA to this
node, so it reflects the actual topology of the system.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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As a first example, add device tree and bindings for the
RealView PB1176.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This implements basic device tree boot support for the RealView
platforms, with a basic device tree for ARM PB1176 as an example.
The implementation is done with a new DT-specific board file
using only pre-existing bindings for the basic IRQ, timer and
serial port drivers. A new compatible type is added to the GIC
for the ARM1176.
This implementation uses the MFD syscon handle from day one to
access the system controller registers, and register the devices
using the SoC bus.
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh@kernel.org>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt
Merge "1st Round of Samsung DT updates for v3.19" from Kukjin Kim:
Samsung DT updates for v3.19
- add CPU nodes for exynos4210, exynos4212, exynos4412
- exynos4x12-pinctrl: add utility macro to define pin sleep states
- exynos4412-trats2: add Maxim77693 PMIC node, add sleep mode pin
configuration and keep eMMC regulators soft-disabled
- add new exynos5250-spring DT
- cleanup exynos5250-arndale, exynos5250-smdk5250 and exynos5250-snow
- exynos5250-arndale: fix apparent GPIO typo and simplify USB3503
- exynos5250-snow and exynos Peach boards: add rtc_src clock for RTC
- correct mmc0 capability string exynos5420-peach-pit and exynos5800-
peach-pi
- exynos3250: add MFC codec nodes
- s3c64xx: enable PWM node by default
* tag 'samsung-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: dts: add CPU nodes for Exynos4 SoCs
ARM: dts: add MFC codec device node for exynos3250
ARM: dts: Add Maxim 77693 PMIC to exynos4412-trats2
ARM: dts: Add sleep mode pin configuration for exynos4412-trats2
ARM: dts: Add utility macro to define pin sleep states for exynos4x12-pinctrl
ARM: dts: Keep eMMC regulators soft-disabled for exynos4412-trats2
ARM: dts: correct the mmc0 capability string for exynos Peach boards
ARM: dts: Add rtc_src clk for s3c-rtc on exynos5250-snow
ARM: dts: Add rtc_src clk for s3c-rtc on exynos Peach boards
ARM: dts: Enable PWM node by default for s3c64xx
ARM: dts: Add exynos5250-spring device tree
ARM: dts: Simplify USB3503 on exynos5250-arndale
ARM: dts: Fix apparent GPIO typo in exynos5250-arndale
ARM: dts: Clean up exynos5250-arndale
ARM: dts: Clean up exynos5250-smdk5250
ARM: dts: Fill in bootargs for exynos5250-snow
ARM: dts: Clean up exynos5250-snow
ARM: dts: Prepare node labels for exynos5250
Signed-off-by: Olof Johansson <olof@lixom.net>
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Recent patch by Tomasz Figa ("irqchip: gic: Fix core ID calculation
when topology is read from DT") fixed GIC driver to filter cluster ID
from values returned by cpu_logical_map() for SoCs having registers
mapped without per-CPU banking making it is possible to add CPU nodes
for Exynos4 SoCs. In case of Exynos SoCs these CPU nodes are also
required by future changes adding initialization of cpuidle states in
Exynos cpuidle driver through DT.
Tested on Origen board (Exynos4210 SoC) and Trats2 (Exynos4412 SoC).
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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The MAX77693 is a companion power management IC for smart phones and
tablets.
The MAX77693 contains input over-voltage protection (OVP),
a fully-integrated 2.5A switching charger for Lithium Ion battery with
integrated battery disconnect, OTG/accessory 5V output power,
a high-current white LED driver for camera flash, two safeout LDOs,
a haptic motor driver, Model Gauge m3 battery fuel gauge and MicroUSB
Interface Controller (MUIC). I2C serial interface is used for
communicating.
Add MAX77693 node to the Trats2 board. This allows using:
- charger regulator,
- 2 safeout LDO regulators (for USB OTG),
- extcon.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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This patch adds sleep mode pin configuration using pin control hog
mechanism to configure states of GPIO pins in sleep mode. This is
required to reduce leakage current in sleep mode and prevent glitching
of components on the board.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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This patch adds a convenient macro which constructs an Exynos pinctrl
pinconf node containing properties needed to configure sleep state of
given pin with given parameters. It will be used by further patch which
adds a large number of sleep states for pins that need such
configuration on certain boards.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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In MAX77686 PMIC two regulators dedicated for eMMC memory can be
controlled both by I2C interface and a GPIO pin, with the resulting
regulator state being a logical OR of both. Since the GPIO control is
used both by the kernel and the lowest level bootloader at reset, the
regulator should be disabled by I2C control to allow it to be turned off
by GPIO control.
This patch removes regulator-always-on properties from both regulators
and, while at it, also unsupported regulator-mem-off.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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