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* ARM: ux500: Rename MSP board file to something more meaningfulLee Jones2012-09-20
| | | | | | | | | | | | The 'msp' board file does more than just register MSP devices. It also registers some other components necessary to get audio working on ux500 based platforms; such as the PCM and Machine Drivers. For that reason we're changing the filename to be more encompassing - 'audio'. Acked-by: Ola Lilja <ola.o.lilja@stericsson.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* ARM: ux500: Remove platform registration of MSP devicesLee Jones2012-09-20
| | | | | | | | | | This patch removes platform device registration of all 4 MSP devices. It also takes care of all redundant infrastructure now that each of the ux500 audio components have been Device Tree enabled. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* ARM: ux500: Stop registering the MOP500 Audio driver from platform codeLee Jones2012-09-20
| | | | | | | | In this patch we prevent MOP500 driver registration from platform code and rely solely on Device Tree to do the probing for us. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* ARM: ux500: Pass MSP DMA platform data though AUXDATALee Jones2012-09-20
| | | | | | | | | | | It isn't currently possible to pass all platform specific configuration though Device Tree. Thinks like device names used in the clock infrastructure, call-backs and DMA information have to be passed in via AUXDATA structures and the MSP is no exception. Here we're passing DMA settings. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* ARM: ux500: Fork MSP platform registration for step-by-step DT enablementLee Jones2012-09-20
| | | | | | | | | | | We've done this before and it worked well last time. Here we're duplicating a complex registration function to ease the process of enabling it for Device Tree. As there are quite a few steps taken during the registration process, it makes sense to break them up into more manageable chunks. This patch will aid us. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* ARM: ux500: Add AB8500 CODEC node to DB8500 Device TreeLee Jones2012-09-20
| | | | | | | | Ensure correct probing and pass though important configuration options to the AB8500 CODEC driver when DT is enabled Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* ARM: ux500: Clean-up MSP platform codeLee Jones2012-09-20
| | | | | | | | | | This patch contains a couple of general MSP clean-ups pertaining to layout changes and changing functions to be void instead of int instead of regardlessly returning '0'. Acked-by: Ola Lilja <ola.o.lilja@stericsson.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* ARM: ux500: Pass SDI DMA information though AUX_DATA to MMCILee Jones2012-09-20
| | | | | | | | | There are four SDIs on the HREF, as opposed to the original two enabled on Snowball. To get them working we have to pass their DMA information in the same was as we need with the other two. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* ARM: ux500: Add UART support to the HREF Device TreeLee Jones2012-09-20
| | | | | | | | Here we add three nodes enabling UART support on the HREF hardware reference board. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* ARM: ux500: Add skeleton Device Tree for the HREF reference boardLee Jones2012-09-20
| | | | | | | | First commit applying the new Device Tree for ST-Ericsson's u8500 based hardware reference board. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* ARM: ux500: Add i2c configurations to the Device Tree for DB8500 based devicesLee Jones2012-09-20
| | | | | | | | | | | | | | Since initial support was provided for the Nomadik I2C driver, it has been converted to an AMBA device. AMBA devices are probed in a slightly different way to other devices, so we have to identify them using an "arm,primecell" compatible string. As well as doing just that, this patch specifies which regulators the controller should use and requests a clock-speed. The latter is provided as more of an example, as it's the same as the recently changed default configuration. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* ARM: ux500: Match Power-On-Key MFD and DTS compatible stringsLee Jones2012-09-20
| | | | | | | | | | The compatible string found in the Power-On-Key's MFD cell matches the device name provided in the driver. Keeping this naming convention seems like a good idea, so we're changing the one found in the DTS file to match. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* ARM: ux500: Remove unused snowball_of_platform_devs structLee Jones2012-09-20
| | | | | | | | | This was left over during a recent clean-up which removed Device Tree helper structs. There is no longer a requirement for it, so we can just remove it. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* ARM: ux500: Force AB8500 to use the GIC as its interrupt controllerLee Jones2012-09-20
| | | | | | | | | | | | It's understood that the AB8500 should be subordinate to the DB8500; however, the AB8500 uses the GIC as it's interrupt controller. If we do not specify which IRQ controller to use the default is to use the next encountered IRQ controller as we climb the tree. This would be the DB8500. This patch ensures the AB8500 makes use of the correct interrupt controller. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* ARM: ux500: Identify the PRCMU as an interrupt controllerLee Jones2012-09-20
| | | | | | | | | | We're just about to provide the DB8500-PRCMU with its own IRQ domain, so that its subordinate drivers can use it as an interrupt controller. It's obligatory for all IRQ controllers to reference themselves as such from its own node in Device Tree. This patch does just that. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* ARM: ux500: Pass PMU platform data due for Perf though AUXDATALee Jones2012-09-20
| | | | | | | | | | | | When booting with Device Tree we need a way to call-back to the DB8500 PMU IRQ handler. This is necessary because the two CPU IRQ lines are muxed together on the DB8500 chip. The DB8500 PMU IRQ handler contains logic to pass over to the other core in the case of IRQ_NONE. This patch allows the DB8500 PMU IRQ handler to be passed to Perf through platform data. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* ARM: ux500: Clean-up temporary Device Tree enablement helpersLee Jones2012-09-20
| | | | | | | | Here we remove some of the extra overhead we introduced to make DT:ing the Snowball platform easier. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* ARM: ux500: Rename db8500.dtsi to dbx5x0.dtsi to encompass the u9500, u8540 ↵Lee Jones2012-09-20
| | | | | | | and u9540 Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* ASoC: Ux500: Move MSP pinctrl setup into the MSP driverLee Jones2012-09-20
| | | | | | | | | | | | | In the initial submission of the MSP driver msp1 and msp3's associated pinctrl mechanism was passed back to platform code using a plat_init() call-back routine, but it has no place in platform code. The MSP driver should set this up for the appropriate ports. Instead we use a use_pinctrl identifier which is passed from platform_data/Device Tree which indicates which ports should use pinctrl. Acked-by: Ola Lilja <ola.o.lilja@stericsson.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* Merge branch 'fixes-for-3.6' of ↵Linus Torvalds2012-09-14
|\ | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mszyprowski/linux-dma-mapping Pull one more DMA-mapping fix from Marek Szyprowski: "This patch fixes very subtle bug (typical off-by-one error) which might appear in very rare circumstances." * 'fixes-for-3.6' of git://git.linaro.org/people/mszyprowski/linux-dma-mapping: arm: mm: fix DMA pool affiliation check
| * arm: mm: fix DMA pool affiliation checkThomas Petazzoni2012-09-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The __free_from_pool() function was changed in e9da6e9905e639b0f842a244bc770b48ad0523e9. Unfortunately, the test that checks whether the provided (start,size) is within the DMA pool has been improperly modified. It used to be: if (start < coherent_head.vm_start || end > coherent_head.vm_end) Where coherent_head.vm_end was non-inclusive (i.e, it did not include the first byte after the pool). The test has been changed to: if (start < pool->vaddr || start > pool->vaddr + pool->size) So now pool->vaddr + pool->size is inclusive (i.e, it includes the first byte after the pool), so the test should be >= instead of >. This bug causes the following message when freeing the *first* DMA coherent buffer that has been allocated, because its virtual address is exactly equal to pool->vaddr + pool->size : WARNING: at /home/thomas/projets/linux-2.6/arch/arm/mm/dma-mapping.c:463 __free_from_pool+0xa4/0xc0() freeing wrong coherent size from pool Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Marek Szyprowski <m.szyprowski@samsung.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Lior Amsalem <alior@marvell.com> Cc: Maen Suleiman <maen@marvell.com> Cc: Tawfik Bayouk <tawfik@marvell.com> Cc: Shadi Ammouri <shadi@marvell.com> Cc: Eran Ben-Avi <benavi@marvell.com> Cc: Yehuda Yitschak <yehuday@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> [m.szyprowski: rebased onto v3.6-rc5 and resolved conflict] Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
* | Merge tag 'fixes-for-linus' of ↵Linus Torvalds2012-09-13
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull arm-soc bug fixes from Olof Johansson: - A set of OMAP fixes, about half of them PM/clock related, the rest scattered over the platform code but all small and targeted to real bugs. - Two small i.MX fixes for SSI device clock setup. * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: clk-imx35: Fix SSI clock registration ARM: clk-imx25: Fix SSI clock registration ARM: OMAP4: Fix array size for irq_target_cpu ARM: OMAP4: hwmod data: temporarily comment out data for the sl2if IP block ARM: OMAP: hwmod code: Disable module when hwmod enable fails ARM: OMAP3: hwmod data: fix iva2 reset info ARM: OMAP3xxx: clockdomain: fix software supervised wakeup/sleep ARM: OMAP2+: am33xx: Fix the timer fck clock naming convention ARM: OMAP: Config fix for omap3-touchbook board ARM: OMAP: sram: skip the first 16K on OMAP3 HS ARM: OMAP: sram: fix OMAP4 errata handling ARM: OMAP: timer: obey the !CONFIG_OMAP_32K_TIMER
| * \ Merge tag 'imx-fixes' of git://git.pengutronix.de/git/imx/linux-2.6 into fixesOlof Johansson2012-09-13
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM: i.MX: Fix SSI clock associations for i.MX25/i.MX35 * tag 'imx-fixes' of git://git.pengutronix.de/git/imx/linux-2.6: ARM: clk-imx35: Fix SSI clock registration ARM: clk-imx25: Fix SSI clock registration + Linux 3.6-rc5
| | * | ARM: clk-imx35: Fix SSI clock registrationFabio Estevam2012-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SSI block has two types of clock: ipg: bus clock, the clock needed for accessing registers. per: peripheral clock, the clock needed for generating the bit rate. Currently SSI driver only supports slave mode and only need to handle the ipg clock, because the peripheral clock comes from the master codec. Only register the ipg clock and do not register the peripheral clock for ssi. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Cc: stable@vger.kernel.org
| | * | ARM: clk-imx25: Fix SSI clock registrationFabio Estevam2012-09-11
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SSI block has two types of clock: ipg: bus clock, the clock needed for accessing registers. per: peripheral clock, the clock needed for generating the bit rate. Currently SSI driver only supports slave mode and only need to handle the ipg clock, because the peripheral clock comes from the master codec. Only register the ipg clock and do not register the peripheral clock for ssi. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Cc: stable@vger.kernel.org
| * | Merge tag 'omap-fixes-for-v3.6-rc4' of ↵Olof Johansson2012-09-07
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes Fixes for timer, sram, memory corruption, and one board file that affect booting on various omaps. Then some PM related fixes for reset, sleep and wakeup. * tag 'omap-fixes-for-v3.6-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP4: Fix array size for irq_target_cpu ARM: OMAP4: hwmod data: temporarily comment out data for the sl2if IP block ARM: OMAP: hwmod code: Disable module when hwmod enable fails ARM: OMAP3: hwmod data: fix iva2 reset info ARM: OMAP3xxx: clockdomain: fix software supervised wakeup/sleep ARM: OMAP2+: am33xx: Fix the timer fck clock naming convention ARM: OMAP: Config fix for omap3-touchbook board ARM: OMAP: sram: skip the first 16K on OMAP3 HS ARM: OMAP: sram: fix OMAP4 errata handling ARM: OMAP: timer: obey the !CONFIG_OMAP_32K_TIMER
| | * \ Merge tag 'omap-fixes-a-for-3.6rc' of ↵Tony Lindgren2012-09-05
| | |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into fixes Some hwmod, clockdomain, am335x fixes against v3.6-rc4. Test logs can be found here: http://www.pwsan.com/omap/testlogs/omap_fixes_a_3.6rc/20120904110254/
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| | | *-. \ Merge branches 'clkdev_fixes_3.6rc', 'clkdm_fixes_3.6rc' and ↵Paul Walmsley2012-09-03
| | | |\ \ \ | | | | | | | | | | | | | | | | | | | | | 'hwmod_data_fixes_a_3.6rc' into omap_fixes_a_3.6rc
| | | | | * | ARM: OMAP4: hwmod data: temporarily comment out data for the sl2if IP blockTero Kristo2012-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OMAP4 sl2if IP block requires some special programming for it to enter idle. Without this programming, it will prevent the rest of the chip from entering full chip idle. This patch comments out the IP block data. Later, once the appropriate support is available, this patch can be reverted. Cc: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | | | * | ARM: OMAP: hwmod code: Disable module when hwmod enable failsMisael Lopez Cruz2012-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clock and module mode are explictly enable when hwmod is enabled. But if the hwmod doesn't get ready on time, clocks are disabled but module is left enabled. Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | | | * | ARM: OMAP3: hwmod data: fix iva2 reset infoTero Kristo2012-09-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IVA2 hwmod resets were missing the status bit offsets. Also, as the hwmod itself didn't have prcm info at all, resetting iva hwmod was accessing some bogus memory addresses. Added both infos to fix this. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | | * | | ARM: OMAP3xxx: clockdomain: fix software supervised wakeup/sleepPaul Walmsley2012-09-03
| | | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 4da71ae6 ("OMAP: clockdomain: Arch specific funcs for clkdm_clk_enable/disable") called the OMAP2xxx-specific functions for clockdomain wakeup and sleep. This would probably have broken software-supervised clockdomain wakeup and sleep on OMAP3. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Jon Hunter <jon-hunter@ti.com> Acked-by: Rajendra Nayak <rnayak@ti.com>
| | | * / / ARM: OMAP2+: am33xx: Fix the timer fck clock naming conventionVaibhav Hiremath2012-09-03
| | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With commit ae6df418a21f3a361c5f9b878e32a8aba4e17692 Sub: ARM: OMAP2+: dmtimer: cleanup fclk usage) The Timer functional clock naming convention has changed from gptX_fck => timerXfck, and so as the timer init function in mach-omap2/timer.c. OMAP4 clocktree also has changed accordingly. AM33xx Clock Tree has been merged during rc3-4 timeframe, before above commit got merged, so similar change is required for AM33xx as well (Change the gptX_fck => timerX_fck). Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | | Merge branch 'fixes-wakeupgen' into fixesTony Lindgren2012-09-05
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| | | * | | ARM: OMAP4: Fix array size for irq_target_cpuTony Lindgren2012-09-04
| | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If NR_IRQS is less than MAX_IRQS, we end up writing past the irq_target_cpu array in omap_wakeupgen_init(): /* Associate all the IRQs to boot CPU like GIC init does. */ for (i = 0; i < max_irqs; i++) irq_target_cpu[i] = boot_cpu; This can happen if SPARSE_IRQ is enabled as by default NR_IRQS is set to 16. Without this patch we're overwriting other data during the boot. Looks like a similar fix was posted by Benoit Cousson earlier as "ARM: OMAP2+: wakeupgen: Fix wrong array size for irq_target_cpu" but was lost. Cc: stable@vger.kernel.org Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | ARM: OMAP: Config fix for omap3-touchbook boardRadek Pilar2012-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix inconsistency between mach-types and CONFIG_ name that prevents touchbook board from booting. Signed-off-by: Radek Pilar <mrkva@mrkva.eu> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | ARM: OMAP: sram: skip the first 16K on OMAP3 HSAaro Koskinen2012-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some OMAP3 HS devices (at least Nokia N9 and N950), the public SRAM seems to conflict with secure portition of SRAM. When booting the 3.6-rc3 kernel (and also earlier) on these devices, the kernel gets tainted with tons of the following warnings: [ 6.894348] In-band Error seen by MPU at address 0 [...] [ 6.894378] WARNING: at arch/arm/mach-omap2/omap_l3_smx.c:162 Fix this by skipping the first 16K of the public SRAM. (Note that the mapping could not be changed, as it resulted in secure monitor call failure in save_secure_sram().) This will leave 12K SRAM available that should be still sufficient. The patch has been boot tested with vanilla 3.6-rc3 on N900, N950 and N9. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | ARM: OMAP: sram: fix OMAP4 errata handlingAaro Koskinen2012-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP4-specific code should be executed only if we are running on OMAP4. Otherwise it may break multi-OMAP kernels. Found by reading the code. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | ARM: OMAP: timer: obey the !CONFIG_OMAP_32K_TIMERIgor Grinberg2012-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, omap2_sync32k_clocksource_init() function initializes the 32K timer as the system clock source regardless of the CONFIG_OMAP_32K_TIMER setting. Fix this by providing a default implementation for !CONFIG_OMAP_32K_TIMER case. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Reviewed-by: Paul Walmsley <paul@pwsan.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: stable@vger.kernel.org Signed-off-by: Tony Lindgren <tony@atomide.com>
* | | | | Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-armLinus Torvalds2012-09-12
|\ \ \ \ \ | |_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM fixes from Russell King: "It's been a while... so there's a little more here than normal. Mostly updates from Will for the breakpoint stuff, and plugging a few holes in the user access functions which crept in when domain support was disabled for ARMv7 CPUs." * 'fixes' of git://git.linaro.org/people/rmk/linux-arm: ARM: 7529/1: delay: set loops_per_jiffy when moving to timer-based loop ARM: 7528/1: uaccess: annotate [__]{get,put}_user functions with might_fault() ARM: 7527/1: uaccess: explicitly check __user pointer when !CPU_USE_DOMAINS ARM: 7526/1: traps: send SIGILL if get_user fails on undef handling path ARM: 7521/1: Fix semihosting Kconfig text ARM: 7513/1: Make sure dtc is built before running it ARM: 7512/1: Fix XIP build due to PHYS_OFFSET definition moving ARM: 7499/1: mm: Fix vmalloc overlap check for !HIGHMEM ARM: 7503/1: mm: only flush both pmd entries for classic MMU ARM: 7502/1: contextidr: avoid using bfi instruction during notifier ARM: 7501/1: decompressor: reset ttbcr for VMSA ARMv7 cores ARM: 7497/1: hw_breakpoint: allow single-byte watchpoints on all addresses ARM: 7496/1: hw_breakpoint: don't rely on dfsr to show watchpoint access type ARM: Fix ioremap() of address zero
| * | | | ARM: 7529/1: delay: set loops_per_jiffy when moving to timer-based loopWill Deacon2012-09-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The delay functions may be called by some platforms between switching to the timer-based delay loop but before calibration. In this case, the initial loops_per_jiffy may not be suitable for the timer (although a compromise may be achievable) and delay times may be considered too inaccurate. This patch updates loops_per_jiffy when switching to the timer-based delay loop so that delays are consistent prior to calibration. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 7528/1: uaccess: annotate [__]{get,put}_user functions with might_fault()Will Deacon2012-09-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The user access functions may generate a fault, resulting in invocation of a handler that may sleep. This patch annotates the accessors with might_fault() so that we print a warning if they are invoked from atomic context and help lockdep keep track of mmap_sem. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 7527/1: uaccess: explicitly check __user pointer when !CPU_USE_DOMAINSRussell King2012-09-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The {get,put}_user macros don't perform range checking on the provided __user address when !CPU_HAS_DOMAINS. This patch reworks the out-of-line assembly accessors to check the user address against a specified limit, returning -EFAULT if is is out of range. [will: changed get_user register allocation to match put_user] [rmk: fixed building on older ARM architectures] Reported-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Cc: stable@vger.kernel.org Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 7526/1: traps: send SIGILL if get_user fails on undef handling pathWill Deacon2012-09-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | get_user may fail to load from the provided __user address due to an unhandled fault generated by the access. In the case of the undefined instruction trap, this results in failure to load the faulting instruction, in which case we should send SIGILL to the task rather than continue with potentially uninitialised data. Signed-off-by: Will Deacon <will.deacon@arm.com> Cc: stable@vger.kernel.org Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 7521/1: Fix semihosting Kconfig textStephen Boyd2012-09-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It seems we were missing some text in the title for the semihosting DEBUG_LL option. Add in the "/O" and fix up some minor typos in the help text. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 7513/1: Make sure dtc is built before running itDavid Brown2012-09-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'make dtbs' in a clean tree will try running the dtc before actually building it. Make these rules depend upon the scripts to build it. Cc: <stable@vger.kernel.org> Signed-off-by: David Brown <davidb@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 7512/1: Fix XIP build due to PHYS_OFFSET definition movingStephen Boyd2012-09-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During the p2v changes, the PHYS_OFFSET #define moved into a !__ASSEMBLY__ section. This causes a XIP build to fail with arch/arm/kernel/head.o: In function 'stext': arch/arm/kernel/head.S:146: undefined reference to 'PHYS_OFFSET' Momentarily leave the #ifndef __ASSEMBLY__ section so we can define PHYS_OFFSET for all compilation units. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 7499/1: mm: Fix vmalloc overlap check for !HIGHMEMJonathan Austin2012-08-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With !HIGHMEM, sanity_check_meminfo checks for banks that completely or partially overlap the vmalloc region. The test for partial overlap checks __va(bank->start + bank->size) > vmalloc_min. This is not appropriate if there is a non-linear translation between virtual and physical addresses, as bank->start + bank->size is actually in the bank following the one being interrogated. In most cases, even when using SPARSEMEM, this is not problematic as the subsequent bank will start at a higher va than the one in question. However if the physical to virtual address conversion is not monotonic increasing, the incorrect test could result in a bank not being truncated when it should be. This patch ensures we perform the va-pa conversion on memory from the bank we are interested in, not the following one. Reported-by: ??? (Steve) <zhanzhenbo@gmail.com> Signed-off-by: Jonathan Austin <jonathan.austin@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 7503/1: mm: only flush both pmd entries for classic MMUWill Deacon2012-08-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LPAE does not use two pmd entries for a pte, so the additional tlb flushing is not required. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 7502/1: contextidr: avoid using bfi instruction during notifierWill Deacon2012-08-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bfi instruction is not available on ARMv6, so instead use an and/orr sequence in the contextidr_notifier. This gets rid of the assembler error: Assembler messages: Error: selected processor does not support ARM mode `bfi r3,r2,#0,#8' Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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