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* ARM: 7029/1: Make cpu_architecture into a global variableDave Martin2011-10-17
| | | | | | | | | | | | The CPU architecture really should not be changing at runtime, so make it a global variable instead of a function. The cpu_architecture() function declared in <asm/system.h> remains the correct way to read this variable from C code. Signed-off-by: Dave Martin <dave.martin@linaro.org> Reviewed-by: Jon Medhurst <tixy@yxit.co.uk> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7022/1: allow to detect conflicting zreladdrsSascha Hauer2011-10-17
| | | | | | | | | | | Boards used to specify zreladdr in their Makefile.boot with zreladdr-y := x, so conflicting zreladdrs were silently overwritten. This patch changes this to zreladdr-y += x, so that we end up with multiple words in zreladdr in such a case. We can detect this later and complain if necessary. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7021/1: Check for multiple load addresses before building a uImageSascha Hauer2011-10-17
| | | | | | | | | | | uImages need a load address specified. This makes them incompatible with multiple zreladdrs. Catch this error before building an uImage so that we do not end up with broken uImages. The load address can still be specified with LOADADDR= on the command line. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7020/1: Check for multiple zreladdrsSascha Hauer2011-10-17
| | | | | | | | | Without CONFIG_AUTO_ZRELADDR being set the kernel needs a single zreladdr for building zImages. Bail out if we detect multiple zreladdrs without CONFIG_AUTO_ZRELADDR. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7006/1: Migrate to asm-generic wrapper supportStephen Boyd2011-10-17
| | | | | | | | | | | | | With d8ecc5c (kbuild: asm-generic support, 2011-04-27) we can remove a handful of asm-generic wrappers in ARM code. Since the generic version of sizes.h doesn't contain SZ_48M, we replace the 4 users of SZ_48M with the equivalent SZ_32M + SZ_16M. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Imre Kaloz <kaloz@openwrt.org> Acked-by: Krzysztof Halasa <khc@pm.waw.pl> Cc: Eric Miao <eric.y.miao@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7088/1: entry: fix wrong parameter name used in do_thumb_abortJanusz Krzysztofik2011-09-10
| | | | | | | | | | | | | | | Commit be020f8618ca, "ARM: entry: abort-macro: specify registers to be used for macros", while replacing register numbers with macro parameter names, mismatched the name used for r1. For me, this resulted in user space built for EABI with -march=armv4t -mtune=arm920t -mthumb-interwork -mthumb broken on my OMAP1510 based Amstrad Delta (old ABI and no thumb still worked for me though). Fix this by using correct parameter name fsr instead of mismatched psr, used by callers for another purpose. Signed-off-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7080/1: l2x0: make sure I&D are not locked down on initLinus Walleij2011-09-06
| | | | | | | | | | | | | | | | | | | Fighting unfixed U-Boots and other beasts that may the cache in a locked-down state when starting the kernel, we make sure to disable all cache lock-down when initializing the l2x0 so we are in a known state. Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Rabin Vincent <rabin.vincent@stericsson.com> Cc: Adrian Bunk <adrian.bunk@movial.com> Cc: Rob Herring <robherring2@gmail.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reported-by: Jan Rinze <janrinze@gmail.com> Tested-by: Robert Marklund <robert.marklund@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7081/1: mach-integrator: fix the clocksourceLinus Walleij2011-09-06
| | | | | | | | | | | | | I was intrigued by the fact that the clock stood still on the Integrator, but it wasn't strange at all, because the timer was set up all wrong and probably has been for a while. With this patch the clock starts ticking again: make the timer periodic (reload), |= on the divisor bit and load the timer before starting it. Cc: stable@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7067/1: mm: keep significant bits in pfn_validMark Rutland2011-09-04
| | | | | | | | | | | | | | | | | | When ARCH_HAS_HOLES_MEMORYMODEL is selected, pfn_valid calls memblock_is_memory to test validity of a pfn: > memblock_is_memory(pfn << PAGE_SHIFT); On LPAE systems this cuts off the top bits, as the shift occurs before the value is promoted to a phys_addr_t. This patch replaces the shift with a call to __pfn_to_phys (which casts pfn to phys_addr_t before shifting), preventing the loss of significant bits. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'fixes' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2011-08-29
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm: ARM: pm: avoid writing the auxillary control register for ARMv7 ARM: pm: some ARMv7 requires a dsb in resume to ensure correctness ARM: pm: arm920/926: fix number of registers saved ARM: pm: CPU specific code should not overwrite r1 (v:p offset) ARM: 7066/1: proc-v7: disable SCTLR.TE when disabling MMU ARM: 7065/1: kexec: ensure new kernel is entered in ARM state ARM: 7003/1: vexpress: Add clock definition for the SP805. ARM: 7051/1: cpuimx* boards: fix mach-types errors ARM: 7019/1: Footbridge: select CLKEVT_I8253 for ARCH_NETWINDER ARM: 7015/1: ARM errata: Possible cache data corruption with hit-under-miss enabled ARM: 7014/1: cache-l2x0: Fix L2 Cache size calculation. ARM: 6967/1: ep93xx: ts72xx: fix board model detection ARM: 6965/1: ep93xx: add model detection for ts-7300 and ts-7400 boards ARM: cache: detect VIPT aliasing I-cache on ARMv6 ARM: twd: register clockevents device before enabling PPI ARM: realview: ensure visibility of writes during reset ARM: perf: make name of arm_pmu_type consistent ARM: perf: fix prototype of release_pmu ARM: fix perf build with uclibc toolchains
| * ARM: pm: avoid writing the auxillary control register for ARMv7Russell King2011-08-28
| | | | | | | | | | | | | | | | | | For ARMv7 kernels running in the non-secure world, writing to the auxillary control register causes an abort, so we must avoid directly writing the auxillary control register. If the ACR has already been reinitialized by SoC code, don't try to restore it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: pm: some ARMv7 requires a dsb in resume to ensure correctnessRussell King2011-08-28
| | | | | | | | | | | | | | Add a dsb after the isb to ensure that the previous writes to the CP15 registers take effect before we enable the MMU. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: pm: arm920/926: fix number of registers savedRussell King2011-08-28
| | | | | | | | | | | | | | ARM920 and ARM926 save four registers, not three. Fix the size of the suspend region required. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: pm: CPU specific code should not overwrite r1 (v:p offset)Russell King2011-08-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r1 stores the v:p offset from the CPU invariant resume code, and is expected to be preserved by the CPU specific code. Overwriting it is not a good idea. We've managed to get away with it on sa1100 platforms because most happen to have PHYS_OFFSET == PAGE_OFFSET, but that may not be the case depending on kernel configuration. So fix this latent bug. This fixes xsc3 as well which was saving and restoring this register independently. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7066/1: proc-v7: disable SCTLR.TE when disabling MMUWill Deacon2011-08-28
| | | | | | | | | | | | | | | | | | | | | | | | cpu_v7_reset disables the MMU and then branches to the provided address. On Thumb-2 kernels, we should take care to clear the Thumb Exception enable bit in the System Control Register, otherwise this may wreak havok in the code to which we are branching (for example, an ARM kernel image via kexec). Reviewed-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7065/1: kexec: ensure new kernel is entered in ARM stateWill Deacon2011-08-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 540b5738 ("ARM: 6999/1: head, zImage: Always Enter the kernel in ARM state") mandates that the kernel should be entered in ARM state. If a Thumb-2 kernel kexecs a new kernel image, we need to ensure that we change state when branching to the new code. This patch replaces a mov pc, lr with a bx lr on Thumb-2 kernels so that we transition to ARM state if need be. Reviewed-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7003/1: vexpress: Add clock definition for the SP805.Nick Bowler2011-08-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It seems that an entry for the SP805 watchdog in the table of clocks was missing. This results in the sp805_wdt driver rejecting the device with the following errors: sp805-wdt mb:wdt: Clock not found sp805-wdt mb:wdt: Probe Failed!!! sp805-wdt: probe of mb:wdt failed with error -2 While not obviously stated in the hardware docs, the onboard SP810's "REFCLK" is connected to a 32.768KHz crystal, and this drives the watchdog. Add a struct clk and corresponding lookup entry for it. Signed-off-by: Nick Bowler <nbowler@elliptictech.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7051/1: cpuimx* boards: fix mach-types errorsEric Bénard2011-08-22
| | | | | | | | | | | | | | | | | | I made some changes to the entry in the ARM Machine Registry after submission which was the wrong thing to do. This patch should help to fix this error. Signed-off-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7019/1: Footbridge: select CLKEVT_I8253 for ARCH_NETWINDERAxel Lin2011-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 8560a6cfc9818edde1fd8677961714b264ffa03d "arm: Footbridge: Use common i8253 clockevent", ARCH_NETWINDER needs to select CLKEVT_I8253. This patch fixes below build error with "make netwinder_defconfig". LD .tmp_vmlinux1 arch/arm/mach-footbridge/built-in.o: In function `isa_timer_init': isa-rtc.c:(.init.text+0x12c8): undefined reference to `clockevent_i8253_init' isa-rtc.c:(.init.text+0x12d0): undefined reference to `i8253_clockevent' arch/arm/mach-footbridge/built-in.o:(.data+0x198): undefined reference to `i8253_clockevent' make: *** [.tmp_vmlinux1] Error 1 Signed-off-by: Axel Lin <axel.lin@gmail.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7015/1: ARM errata: Possible cache data corruption with hit-under-miss ↵Catalin Marinas2011-08-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | enabled This patch is a workaround for the 364296 ARM1136 r0p2 erratum (possible cache data corruption with hit-under-miss enabled). It sets the undocumented bit 31 in the auxiliary control register and the FI bit in the control register, thus disabling hit-under-miss without putting the processor into full low interrupt latency mode. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7014/1: cache-l2x0: Fix L2 Cache size calculation.Srinivas Kandagatla2011-08-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes L2 Cache size calculations for L2C-210, L2C-310 and PL310, by changing the L2X0_AUX_CTRL_WAY_SIZE_MASK from 2 bits to 3 bits. The Auxiliary Control Register for L2C-210, L2C-310 and PL310 has 3bits [19:17] for Way size, however the existing code only uses 2 bits to get this value. This results in incorrect cachesize calculations. It also results in performing operations on the whole cache when we erroneously decide that the range is big enough (due to l2x0_size being too small) and also prints incorrect cachesize. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Acked-by: Will Deacon <will.deacon@arm.com> Cc: stable@kernel.org Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 6967/1: ep93xx: ts72xx: fix board model detectionPetr Štetiar2011-08-15
| | | | | | | | | | | | | | | | | | | | | | Fix the obvious error in board detection logic, because according to the TS's manual, the model is stored in the least three significant bits. For example the byte read on my ts-7300 is 0x23 and the detection then fails. Cc: Ryan Mallon <ryan@bluewatersys.com> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Petr Štetiar <ynezz@true.cz> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 6965/1: ep93xx: add model detection for ts-7300 and ts-7400 boardsPetr Štetiar2011-08-15
| | | | | | | | | | | | | | Cc: Ryan Mallon <ryan@bluewatersys.com> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Petr Štetiar <ynezz@true.cz> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * Merge branch '3.1-fixes-for-rmk' of git://linux-arm.org/linux-2.6-wd into fixesRussell King2011-08-13
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| | * ARM: cache: detect VIPT aliasing I-cache on ARMv6Will Deacon2011-08-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current cache detection code does not check for an aliasing I-cache if the D-cache is found to be VIPT aliasing. This patch fixes the problem by always checking for an aliasing I-cache on v6 and later. Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * ARM: twd: register clockevents device before enabling PPIWill Deacon2011-08-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The smp_twd clockevents driver currently enables the local timer PPI before the clockevents device is registered. This can lead to a kernel panic if a spurious timer interrupt is generated before registration has completed since the kernel will treat it as an IPI timer. This patch moves the clockevents device registration before the IRQ unmasking so that we can always handle timer interrupts once they can occur. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * ARM: realview: ensure visibility of writes during resetWill Deacon2011-08-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The various reset routines in mach-realview rely on an FPGA to power-cycle the board after writing some magic runes to memory-mapped registers. This patch adds a dsb() following the writes, so that they become visible before we mdelay(1000) in the arch_reset code. Without this patch, the timeout would expire sporadically, causing the reset to fail. Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * ARM: perf: make name of arm_pmu_type consistentMark Rutland2011-08-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit f12482c9 ("ARM: 6974/1: pmu: refactor reservation") changed {release,reserve}_pmu to take an enum arm_pmu_type as a parameter, but inconsistently named the parameter `type' or `device'. It would be nice if these were consistent. This patch makes use of enum arm_pmu_type consistent, always using `type'. Related printks are updated, explicitly mentioning `type' also. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * ARM: perf: fix prototype of release_pmuMark Rutland2011-08-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit f12482c9 ("ARM: 6974/1: pmu: refactor reservation") changed the prototype of release_pmu, but missed the stub for when CONFIG_CPU_HAS_PMU is not selected by the platform. This patch changes the prototype of the stub, preventing possible build failures when CONFIG_CPU_HAS_PMU is not selected. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* | | Merge branch 'fixes' of ↵Linus Torvalds2011-08-29
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc * 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: ARM: mach-footbridge: add missing header file <video/vga.h> ARM: mach-orion5x: add missing header file <linux/vga.h> arm: fix compile failure in orion5x/dns323-setup.c at91: at91sam9261.c: fix typo in t2_clk alias for atmel_tcb.0 ARM: S5P: fix bug in spdif_clk_get_rate ARM: EXYNOS4: Add restart hook for proper reboot ARM: EXYNOS4: Increase reset delay for USB HOST PHY ARM: S5P: add required chained_irq_enter/exit to gpio-int code ARM: EXYNOS4: add required chained_irq_enter/exit to eint code ARM: SAMSUNG: Add chained enrty/exit call to timer interrupt handler ARM: S3C64XX: Fix build break in PM debug ARM: S5PV210: Fix build warning ARM: EXYNOS4: Fix the IRQ definitions for MIPI CSIS device ARM: EXYNOS4: remove duplicated inclusion ARM: EXYNOS4: Fix wrong devname to support clkdev ARM: EXYNOS4: Use the correct regulator names on universal_c210 ARM: SAMSUNG: Fix Section mismatch in samsung_bl_set() ARM: S5P64X0: Replace irq_gc_ack() with irq_gc_ack_set_bit()
| * \ \ Merge branch 'at91/fixes' of ↵Arnd Bergmann2011-08-26
| |\ \ \ | | | | | | | | | | | | | | | git+ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc into fixes
| | * | | at91: at91sam9261.c: fix typo in t2_clk alias for atmel_tcb.0Jean-Christophe PLAGNIOL-VILLARD2011-08-24
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was a typo in clockdev declaration for at91sam9261 SoC. Fix the kernel hanging when switching clocksource to TC (tcb_clksrc). Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Remy Bohmer <linux@bohmer.net> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| * | | Merge branch 'fixes' of git://git.jdl.com/software/linux-3.0 into fixesArnd Bergmann2011-08-26
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| | * | | ARM: mach-footbridge: add missing header file <video/vga.h>Bryan Wu2011-08-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes following building error: -- arch/arm/mach-footbridge/dc21285.c: In function 'dc21285_preinit': arch/arm/mach-footbridge/dc21285.c:299:2: error: 'vga_base' undeclared (first use in this function) arch/arm/mach-footbridge/dc21285.c:299:2: note: each undeclared identifier is reported only once for each function it appears in make[1]: *** [arch/arm/mach-footbridge/dc21285.o] Error 1 -- Signed-off-by: Bryan Wu <bryan.wu@canonical.com> Acked-by: Rob Herring <rob.herring@calxeda.com>
| | * | | ARM: mach-orion5x: add missing header file <linux/vga.h>Bryan Wu2011-08-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixed following building error: -- arch/arm/mach-orion5x/pci.c: In function 'orion5x_pci_sys_setup': arch/arm/mach-orion5x/pci.c:563:2: error: 'vga_base' undeclared (first use in this function) arch/arm/mach-orion5x/pci.c:563:2: note: each undeclared identifier is reported only once for each function it appears in make[1]: *** [arch/arm/mach-orion5x/pci.o] Error 1 make[1]: *** Waiting for unfinished jobs.... -- Signed-off-by: Bryan Wu <bryan.wu@canonical.com> Acked-by: Rob Herring <rob.herring@calxeda.com>
| | * | | arm: fix compile failure in orion5x/dns323-setup.cPaul Gortmaker2011-08-25
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upstream commit d5341942d784134f2997b3ff82cd63cf71d1f932 "PCI: Make the struct pci_dev * argument of pci_fixup_irqs const." leaked an extra "const" into an actual call site (vs a proto/decl) which causes this: arch/arm/mach-orion5x/dns323-setup.c: In function 'dns323_pci_map_irq': arch/arm/mach-orion5x/dns323-setup.c:80: error: expected expression before 'const' arch/arm/mach-orion5x/dns323-setup.c:80: error: too few arguments to function 'orion5x_pci_map_irq' make[3]: *** [arch/arm/mach-orion5x/dns323-setup.o] Error 1 Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Nicolas Pitre <nico@fluxnic.net> Acked-by: Ralf Baechle <ralf@linux-mips.org>
| * | | ARM: S5P: fix bug in spdif_clk_get_rateNaveen Krishna Chatradhi2011-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Should be passing the parent clk object when calling for parent rate. Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | ARM: EXYNOS4: Add restart hook for proper rebootKyungmin Park2011-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is required to use SWRESET. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | ARM: EXYNOS4: Increase reset delay for USB HOST PHYYulgon Kim2011-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch increases reset delay from 50 usec to 80 usec for USB HOST PHY. In order to reset USB HOST PHY controller properly, a little extra time is required during its reset cycle. Signed-off-by: Yulgon Kim <yulgon.kim@samsung.com> Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | ARM: S5P: add required chained_irq_enter/exit to gpio-int codeMarek Szyprowski2011-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds chained IRQ enter/exit functions to gpio interrupt handler in order to function correctly on primary controllers with different methods of flow control. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | ARM: EXYNOS4: add required chained_irq_enter/exit to eint codeMarek Szyprowski2011-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds chained IRQ enter/exit functions to external interrupt handler in order to function correctly on primary controllers with different methods of flow control. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | ARM: SAMSUNG: Add chained enrty/exit call to timer interrupt handlerMarek Szyprowski2011-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds chained IRQ enter/exit functions to timer interrupt handler in order to function correctly on primary controllers with different methods of flow control. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | ARM: S3C64XX: Fix build break in PM debugAbhilash Kesavan2011-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When S3C_PM_DEBUG_LED_SMDK is enabled for suspend/resume debugging, the following compilation error occurs: arch/arm/mach-s3c64xx/pm.c: In function 's3c_pm_debug_smdkled': arch/arm/mach-s3c64xx/pm.c:41: error: implicit declaration of function 'gpio_set_value' arch/arm/mach-s3c64xx/pm.c:41: error: implicit declaration of function 'S3C64XX_GPN' arch/arm/mach-s3c64xx/pm.c: In function 's3c64xx_pm_init': arch/arm/mach-s3c64xx/pm.c:184: error: implicit declaration of function 'gpio_request' arch/arm/mach-s3c64xx/pm.c:188: error: implicit declaration of function 'gpio_direction_output' Fix the error by including linux/gpio.h Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | ARM: S5PV210: Fix build warningAbhilash Kesavan2011-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixed the following warning for S5PV210. arch/arm/mach-s5pv210/pm.c: In function 's5pv210_pm_add': arch/arm/mach-s5pv210/pm.c:139: warning: assignment from incompatible pointer type Also, staticized the function. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | ARM: EXYNOS4: Fix the IRQ definitions for MIPI CSIS deviceSylwester Nawrocki2011-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a regression fix after migration to the external GIC. The breakage has been introduced in commit 69644a8e23ab ("ARM: EXYNOS4: modify interrupt mappings for external GIC") Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [kgene.kim@samsung.com: added commit id] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | ARM: EXYNOS4: remove duplicated inclusionHuang Weiyi2011-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove duplicated #include('s) in arch/arm/mach-exynos4/cpu.c Signed-off-by: Huang Weiyi <weiyi.huang@gmail.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | ARM: EXYNOS4: Fix wrong devname to support clkdevJonghwan Choi2011-08-19
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | ARM: EXYNOS4: Use the correct regulator names on universal_c210Kyungmin Park2011-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the correct regulator names for cpufreq Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | ARM: SAMSUNG: Fix Section mismatch in samsung_bl_set()Kukjin Kim2011-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | WARNING: vmlinux.o(.text+0xf47c): Section mismatch in reference from the function samsung_bl_set() to the (unknown reference) .init.data:(unknown) The function samsung_bl_set() references the (unknown reference) __initdata (unknown). This is often because samsung_bl_set lacks a __initdata annotation or the annotation of (unknown) is wrong. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | | ARM: S5P64X0: Replace irq_gc_ack() with irq_gc_ack_set_bit()Kukjin Kim2011-08-19
| |/ / | | | | | | | | | | | | | | | | | | | | | According to commit 659fb32d1b67476f4ade25e9ea0e2642a5b9c4b5 ("replace irq_gc_ack() with {set,clr}_bit variants"), this should be fixed. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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