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* Merge tag 'samsung-update' of ↵Olof Johansson2015-01-29
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc Merge "Samsung mach updates for v3.20" from Kukjin Kim: - add exynos3250 Supsend to RAM support - recognize MFC v8 devices for exynos5422/5800 - print CPU id/rev during kernel boot * tag 'samsung-update' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: Add exynos3250 suspend-to-ram support ARM: EXYNOS: Recognize Samsung MFC v8 devices ARM: SAMSUNG: print CPU id on probe Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: EXYNOS: Add exynos3250 suspend-to-ram supportChanwoo Choi2015-01-14
| | | | | | | | | | | | | | | | | | This patch supports suspend-to-ram for Exynos3250 SoC and the SoC doesn't contain L2 cache. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
| * ARM: EXYNOS: Recognize Samsung MFC v8 devicesSjoerd Simons2015-01-12
| | | | | | | | | | | | | | | | Also setup memory allocations for version 8 of the MFC as present in Samsung Exynos 5422/5800 SoCs Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Kukjin Kim <kgene@kernel.org>
| * ARM: SAMSUNG: print CPU id on probeOlof Johansson2014-12-22
| | | | | | | | | | | | | | | | | | | | It's useful to get the CPU ID/rev printed during boot sometimes, so add a line with that information. Given that the fields have moved within the register over time, don't try to be clever and parse it -- just print the raw values for now. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Kukjin Kim <kgene@kernel.org>
* | ARM: digicolor: select syscon and timerBaruch Siach2015-01-29
| | | | | | | | | | | | | | | | | | | | The digicolor interrupt controller driver now needs syscon. Also, as per clocksource maintainer request, we now have a separate config symbol, CONFIG_DIGICOLOR_TIMER, for the digicolor timer. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Olof Johansson <olof@lixom.net>
* | ARM: digicolor: add low level debug supportBaruch Siach2015-01-27
| | | | | | | | | | | | | | | | | | Use the USART peripheral as UART for low level debug. Only the UA0 port is currently supported. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Olof Johansson <olof@lixom.net>
* | ARM: initial support for Conexant Digicolor CX92755 SoCBaruch Siach2015-01-27
| | | | | | | | | | | | | | | | | | | | Add initial support for the Conexant CX92755 SoC. The CX92755 is one of the Digicolor series of SoCs, all sharing many of the same peripherals. The code was tested on the CX92755 evaluation kit, AKA Equinox. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Olof Johansson <olof@lixom.net>
* | Merge tag 'omap-for-v3.20/dm816x-data' of ↵Olof Johansson2015-01-26
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc Merge "omap changes to make dm816x usable" from Tony Lindgren: Patches to add necessary SoC related clockdomain and interconnect data to make dm816x boot with basic devices. This finally gets dm816x into a usable shape for further work to happen after a few years of stalled effort of making this SoC to work with the mainline kernel. As most of the devices are similar to the other omap variants, we get at least serial, MMC, Ethernet, I2C, EDMA, pinctrl, SPI and GPMC working for these SoCs with the related device tree changes. * tag 'omap-for-v3.20/dm816x-data' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2+: Add dm816x hwmod support ARM: OMAP2+: Add clock domain support for dm816x ARM: OMAP2+: Add board-generic.c entry for ti81xx ARM: OMAP2+: Disable omap3 PM init for ti81xx ARM: OMAP2+: Fix reboot for 81xx ARM: OMAP2+: Fix dm814 and dm816 for clocks and timer init ARM: OMAP2+: Fix ti81xx class type ARM: OMAP2+: Fix ti81xx devtype ARM: OMAP2+: Fix error handling for omap2_clk_enable_init_clocks Signed-off-by: Olof Johansson <olof@lixom.net>
| * | ARM: OMAP2+: Add dm816x hwmod supportTony Lindgren2015-01-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add minimal hwmod support that works at least on dm8168. This is based on the code in the earlier TI CDP tree, and an earlier patch by Aida Mynzhasova <aida.mynzhasova@skitlab.ru>. I've set up things to work pretty much the same way as for am33xx. We are basically using cm33xx.c with a different set of clocks and clockdomains. This code is based on the TI81XX-LINUX-PSP-04.04.00.02 patches published at: http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html Cc: Aida Mynzhasova <aida.mynzhasova@skitlab.ru> Cc: Brian Hutchinson <b.hutchman@gmail.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | ARM: OMAP2+: Add clock domain support for dm816xAida Mynzhasova2015-01-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds required definitions and structures for clockdomain initialization, so omap3xxx_clockdomains_init() was substituted by new ti81xx_clockdomains_init() while early initialization of TI81XX platform. Note that we now need to have 81xx in a separate CONFIG_SOC_TI81XX block instead inside the ifdef block for omap3 to avoid make randconfig build errors. This code is based on the TI81XX-LINUX-PSP-04.04.00.02 patches published at: http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Aida Mynzhasova <aida.mynzhasova@skitlab.ru> [tony@atomide.com: updated to apply, renamed to clockdomains81xx.c, fixed to use am33xx_clkdm_operations, various fixes suggested by Paul Walmsley] Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | ARM: OMAP2+: Add board-generic.c entry for ti81xxTony Lindgren2015-01-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | This allows booting ti81xx boards when a .dts file is in place. Cc: Brian Hutchinson <b.hutchman@gmail.com> Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | ARM: OMAP2+: Disable omap3 PM init for ti81xxTony Lindgren2015-01-14
| | | | | | | | | | | | | | | | | | | | | We cannot use the omap3 pm support on 81xx. Cc: Brian Hutchinson <b.hutchman@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | ARM: OMAP2+: Fix reboot for 81xxTony Lindgren2015-01-14
| | | | | | | | | | | | | | | | | | | | | | | | We are missing proper hooks for 81xx for reboot to work. Cc: Brian Hutchinson <b.hutchman@gmail.com> Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | ARM: OMAP2+: Fix dm814 and dm816 for clocks and timer initTony Lindgren2015-01-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fix dm814 and dm816 clocks and timer init. Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | ARM: OMAP2+: Fix ti81xx class typeTony Lindgren2015-01-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise it will return true for cpu_is_omap34xx() which we don't want for the clocks and hwmod. It's closer to am33xx for the clocks and hwmod than to the omap34xx. We also want to be able to detect 814x and 816x separately as at least the clocks are different with 814x using a apll and 816x using a fapll for the source clocks. Note that we can also remove omap3xxx_clk_init() call as it's wrong and ti81xx are booting in device tree only mode. Cc: Brian Hutchinson <b.hutchman@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | ARM: OMAP2+: Fix ti81xx devtypeTony Lindgren2015-01-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise we get error "Cannot detect omap type!" and many things can fail with following: Unhandled fault: imprecise external abort (0xc06) at 0xc6031fb0 This is because the omap_type is being used to set up th SoC specific functions for omaps. Cc: Brian Hutchinson <b.hutchman@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | ARM: OMAP2+: Fix error handling for omap2_clk_enable_init_clocksTony Lindgren2015-01-14
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to check if we got the clock before trying to do anything with it. Otherwise we will get something like this: Unable to handle kernel paging request at virtual address fffffffe ... [<c04bef78>] (clk_prepare) from [<c00338a4>] (omap2_clk_enable_init_clocks+0x50/0x8) [<c00338a4>] (omap2_clk_enable_init_clocks) from [<c0876838>] (dm816x_dt_clk_init+0) ... Let's add check for the clock and WARN if the init clock was not found. Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | Merge tag 'sunxi-core-for-3.20' of ↵Olof Johansson2015-01-26
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/soc Merge "Allwinner core changes for 3.20" from Maxime Ripard: - Support for the A31s - Adding support for cpufreq using cpufreq-dt * tag 'sunxi-core-for-3.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: ARM: sunxi: Register cpufreq-dt for sun[45678]i ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxi Signed-off-by: Olof Johansson <olof@lixom.net>
| * | ARM: sunxi: Register cpufreq-dt for sun[45678]iChen-Yu Tsai2015-01-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | On sun[45678]i, we have one cluster of identical cores sharing a clock, which is ideal for using cpufreq-dt. Register a platform device for cpufreq-dt. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxiHans de Goede2015-01-05
| |/ | | | | | | | | | | | | | | | | | | So far the A31s is 100% compatible with the A31, still lets do the same as what we've done for the A13 / A10s and give it its own compatible string, in case we need to differentiate later. Signed-off-by: Hans de Goede <hdegoede@redhat.com> [Maxime: Removed unusude CPU_OF_DECLARE_METHOD] Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | Merge tag 'at91-cleanup3' of ↵Olof Johansson2015-01-26
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/soc Merge "at91: cleanup/soc for 3.20 #3 (bis) from Nicolas Ferre: Third batch of cleanup/soc for 3.20: - several fixes and adjustments following the last cleanup batch - removal of some unused Kconfig options - slight PM and pm_idle rework to ease future rework - removal of unneeded mach/system_rev.h * tag 'at91-cleanup3' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91: ARM: at91: pm: remove warning to remove SOC_AT91SAM9263 usage ARM: at91: remove unused mach/system_rev.h ARM: at91: stop using HAVE_AT91_DBGUx ARM: at91: fix ordering of SRAM and PM initialization ARM: at91: sam9: set arm_pm_idle from sam9_dt_device_init ARM: at91: fix sam9n12 and sam9x5 arm_pm_idle ARM: at91: mark const init data with __initconst instead of __initdata ARM: at91: fix PM initialization for newer SoCs ARM: at91: fix Kconfig.debug by adding DEBUG_AT91_UART option Signed-off-by: Olof Johansson <olof@lixom.net>
| * | ARM: at91: pm: remove warning to remove SOC_AT91SAM9263 usageAlexandre Belloni2015-01-26
| | | | | | | | | | | | | | | | | | | | | The SOC_AT91SAM9263 is being removed, stop using it. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| * | ARM: at91: remove unused mach/system_rev.hAlexandre Belloni2015-01-26
| | | | | | | | | | | | | | | | | | | | | mach/system_rev.h is not used, remove it. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| * | ARM: at91: stop using HAVE_AT91_DBGUxAlexandre Belloni2015-01-26
| | | | | | | | | | | | | | | | | | | | | In order to remove SOC_SAM9xxx options, stop using HAVE_AT91_DBGUx. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| * | ARM: at91: fix ordering of SRAM and PM initializationNicolas Ferre2015-01-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | The PM initialization needs internal SRAM for allocating a gen_pool and use it to store its PM code. So we need to have of_platform_populate() before this code. Suggested-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| * | ARM: at91: sam9: set arm_pm_idle from sam9_dt_device_initAlexandre Belloni2015-01-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As all sam9 SoCs are setting arm_pm_idle to at91sam9_idle(), do it from sam9_dt_device_init(). Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Suggested-by: Arnd Bergmann <arnd@arndb.de> [nicolas.ferre@atmel.com: adapt patch to newer series] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| * | ARM: at91: fix sam9n12 and sam9x5 arm_pm_idleAlexandre Belloni2015-01-26
| | | | | | | | | | | | | | | | | | | | | | | | sam9n12 and sam9x5 don't set arm_pm_idle because of an oversight, fix that. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| * | ARM: at91: mark const init data with __initconst instead of __initdataAlexandre Belloni2015-01-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As long as there is no other non-const variable marked __initdata in the same compilation unit it doesn't hurt. If there were one however compilation would fail with error: $variablename causes a section type conflict because a section containing const variables is marked read only and so cannot contain non-const variables. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> [nicolas.ferre@atmel.com: update the paths after having re-arranged the patches] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| * | ARM: at91: fix PM initialization for newer SoCsNicolas Ferre2015-01-26
| | | | | | | | | | | | | | | | | | | | | | | | Newer SoCs: at91sam9x5, at91sam9n12, sama5d3 and sama5d4 embed a DDR controller and have a different PMC status register layout than the at91sam9g45. Create another at91_sam9x5_pm_init() function to match this compatibility. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| * | ARM: at91: fix Kconfig.debug by adding DEBUG_AT91_UART optionNicolas Ferre2015-01-26
| | | | | | | | | | | | | | | | | | | | | | | | The DEBUG_AT91_UART Kconfig option was forgotten when moving the AT91 debug-macro.S file. Add it and use it for the at91.S compilation. Reported-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* | | Merge tag 'qcom-soc-for-3.20-2' of ↵Olof Johansson2015-01-23
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/soc merge "qcom SoC changes for v3.20-2" from Kumar Gala: Qualcomm ARM Based SoC Updates for v3.20-2 * Various bug fixes and minor feature additions to scm code * Added big-endian support to debug MSM uart * Added big-endian support to ARCH_QCOM * Cleaned up some Kconfig options associated with ARCH_QCOM * Added Andy Gross as co-maintainer * tag 'qcom-soc-for-3.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom: MAINTAINERS: Add co-maintainer for ARM/Qualcomm Support ARM: qcom: Drop unnecessary selects from ARCH_QCOM ARM: qcom: Fix SCM interface for big-endian kernels ARM: qcom: scm: Clarify boot interface ARM: qcom: Add SCM warmboot flags for quad core targets. ARM: qcom: scm: Add logging of actual return code from scm call ARM: qcom: scm: Flush the command buffer only instead of the entire cache ARM: qcom: scm: Get cacheline size from CTR ARM: qcom: scm: Fix incorrect cache invalidation ARM: qcom: Select ARCH_SUPPORTS_BIG_ENDIAN ARM: debug: msm: Support big-endian CPUs ARM: debug: Update MSM and QCOM DEBUG_LL help Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | ARM: qcom: Drop unnecessary selects from ARCH_QCOMStephen Boyd2015-01-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't need to force gpiolib on everyone given that it isn't required to actually boot the device and the multiplatform Kconfig already selects ARCH_WANT_OPTIONAL_GPIOLIB. CLKSRC_OF is already selected by CONFIG_ARCH_MULTIPLATFORM too, so we can drop that here. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
| * | | ARM: qcom: Fix SCM interface for big-endian kernelsStephen Boyd2015-01-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The secure environment only runs in little-endian mode, so any buffers shared with the secure environment should have their contents converted to little-endian. We also mark such elements with __le32 to allow sparse to catch such problems. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
| * | | ARM: qcom: scm: Clarify boot interfaceStephen Boyd2015-01-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The secure world only knows about 32-bit wide physical addresses for the boot API. Clarify the kernel interface by explicitly stating a u32 instead of phys_addr_t which could be 32 or 64 bits depending on LPAE or not. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
| * | | ARM: qcom: Add SCM warmboot flags for quad core targets.Lina Iyer2015-01-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Quad core targets like APQ8074, APQ8064, APQ8084 need SCM support set up warm boot addresses in the Secure Monitor. Extend the SCM flags to support warmboot addresses for secondary cores. Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
| * | | ARM: qcom: scm: Add logging of actual return code from scm callOlav Haugan2015-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an error occurs during an scm call the error returned is remapped so we lose the original error code. This means that when an error occurs we have no idea what actually failed within the secure environment. Add a logging statement that will log the actual error code from scm call allowing us to easily determine what caused the error to occur. Signed-off-by: Olav Haugan <ohaugan@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
| * | | ARM: qcom: scm: Flush the command buffer only instead of the entire cacheVikram Mulukutla2015-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | scm_call flushes the entire cache before calling into the secure world. This is both a performance penalty as well as insufficient on SMP systems where the CPUs possess a write-back L1 cache. Flush only the command and response buffers instead, moving the responsibility of flushing any other cached buffer (being passed to the secure world) to callers. Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
| * | | ARM: qcom: scm: Get cacheline size from CTRStephen Boyd2015-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of hardcoding the cacheline size as 32, get the cacheline size from the CTR register. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
| * | | ARM: qcom: scm: Fix incorrect cache invalidationStephen Boyd2015-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cache invalidation in scm_call() correctly rounds down the start address to invalidate the beginning of the cacheline but doesn't properly round up the 'end' address to make it aligned. The last chunk of the buffer won't be invalidated when 'end' is not cacheline size aligned so make sure to invalidate the last few bytes in such situations. It also doesn't do anything about outer caches so make sure to invalidate and flush those as well. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
| * | | ARM: qcom: Select ARCH_SUPPORTS_BIG_ENDIANStephen Boyd2015-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We can run qcom platforms in big-endian mode. Select the option. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
| * | | ARM: debug: msm: Support big-endian CPUsStephen Boyd2015-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the CPU is in big-endian mode these macros will access the hardware incorrectly. Reverse thins as necessary to fix this. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
| * | | ARM: debug: Update MSM and QCOM DEBUG_LL helpStephen Boyd2015-01-19
| | |/ | |/| | | | | | | | | | | | | | | | | | | Add another SoC address for apq8064 and use DEBUG_UART_VIRT instead of DEBUG_UART_BASE because the former actually exists. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
* | | Merge tag 'tegra-for-3.20-soc' of ↵Olof Johansson2015-01-23
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc Merge "ARM: tegra: Core code changes for v3.20" from Thierry Reding: This contains a couple of preparatory patches for 64-bit support. A new feature is implemented in the power-management controller which allows it to switch off the SoC if it overheats. * tag 'tegra-for-3.20-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc: tegra: Add thermal reset (thermtrip) support to PMC ARM: tegra: Add PMC thermtrip programming to Jetson TK1 device tree of: Add descriptions of thermtrip properties to Tegra PMC bindings soc/tegra: pmc: Add Tegra132 support soc/tegra: fuse: Add Tegra132 support soc/tegra: fuse: Constify tegra_fuse_info structures soc/tegra: Add Tegra132 support clocksource: Build Tegra timer on 32-bit ARM only soc/tegra: pmc: restrict compilation of suspend-related support to ARM Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | ARM: tegra: Add PMC thermtrip programming to Jetson TK1 device treeMikko Perttunen2015-01-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the required information to reset the board during an overheating situation to the Jetson TK1 device tree. The thermal reset is handled by the PMC by sending an I2C message to the PMIC. The entries specify the I2C message to be sent. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | clocksource: Build Tegra timer on 32-bit ARM onlyThierry Reding2015-01-09
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of directly using the ARCH_TEGRA Kconfig symbol to enable this driver, add a new, non-user-visible Kconfig symbol (TEGRA_TIMER) which can be selected by the various SoCs. This is useful to disable building the driver on Tegra132 (64-bit ARM) where it doesn't currently compile but also isn't needed (yet). Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | | Merge tag 'imx-soc-3.20' of ↵Olof Johansson2015-01-23
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc Merge "ARM: imx: soc changes for 3.20" from Shawn Guo: The i.MX SoC changes for 3.20: - Add .disable_unused function hook for shared gate clock to ensure the clock tree use count matches the hardware state - Add a deeper idle state for i.MX6SX cpuidle driver powering off the ARM core - One correction on i.MX6Q esai_ipg parent clock setting - Add a missing iounmap call for imx6q_opp_check_speed_grading() - Add missing clocks for VF610 UART4, UART5 and SNVS blocks - Expand VF610 device tree compatible matching table to cover more Vybrid family SoCs - Expand i.MX clk-pllv3 a bit with the shift for frequency multiplier to support Vybrid's USB PLL oddity * tag 'imx-soc-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: clk-imx6q: refine esai_ipg's parent ARM i.MX6q: unmap memory mapped at imx6q_opp_check_speed_grading() ARM: imx: clk-vf610: Add clock for SNVS ARM: imx: clk-vf610: Add clock for UART4 and UART5 ARM: imx: drop CPUIDLE_FLAG_TIME_VALID from cpuidle-imx6sx ARM: imx: support arm power off in cpuidle for i.mx6sx ARM: imx: remove unnecessary setting for DSM ARM: imx: correct the hardware clock gate setting for shared nodes ARM: imx: pllv3: add shift for frequency multiplier ARM vf610: add compatibilty strings of supported Vybrid SoC's Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | ARM: clk-imx6q: refine esai_ipg's parentShengjiu Wang2015-01-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | esai_ipg clock's parent is ahb, not ipg. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM i.MX6q: unmap memory mapped at imx6q_opp_check_speed_grading()Sebastian Andrzej Siewior2015-01-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | imx6q_opp_check_speed_grading() remaps memory to the base variable and never unmaps it. I can't see how this can be of any use later so here I unmap it. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: imx: clk-vf610: Add clock for SNVSSanchayan Maity2015-01-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for clock gating of the SNVS peripheral. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: imx: clk-vf610: Add clock for UART4 and UART5Bhuvanchandra DV2015-01-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for clock gating of UART4 and UART5. We use these UART's in a (not yet mainlined) device tree. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 16:40:21 -0500