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* Hook up LITMUS^RT remote preemption support on ARMBjoern B. Brandenburg2010-11-11
| | | | Call into scheduler state machine in the IPI handler.
* ARM: hookup LITMUS^RT system callsBjoern B. Brandenburg2010-11-11
| | | | | Includes the LITMUS^RT-specifc unistd.h extension and modifies the actual syscall table.
* ARM: Include LITMUS^RT KConfigBjoern B. Brandenburg2010-11-11
| | | | Make the ARM built aware of the LITMUS^RT-specific options.
* ARM: provide get_cycles() for RealView PB11{MP,76} and Cortex-A8Bjoern B. Brandenburg2010-11-11
| | | | | Use the CCNT register to override the default get_cycles() implementation in arch/arm/asm/timex.h. This is useful for overhead measurements and debugging.
* ARM: allow mach/timex.h to define get_cycles()Bjoern B. Brandenburg2010-11-11
| | | | | | Some platforms have access to a cycle coutner (CCNT) register in the CP15 coprocessor. This trivial change will allow such platforms to provide specialized implementations.
* Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2010-10-13
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/home/rmk/linux-2.6-arm: ARM: relax ioremap prohibition (309caa9) for -final and -stable ARM: 6440/1: ep93xx: DMA: fix channel_disable cpuimx27: fix i2c bus selection cpuimx27: fix compile when ULPI is selected ARM: 6435/1: Fix HWCAP_TLS flag for ARM11MPCore/Cortex-A9 ARM: 6436/1: AT91: Fix power-saving in idle-mode on 926T processors ARM: fix section mismatch warnings in Versatile Express ARM: 6412/1: kprobes-decode: add support for MOVW instruction ARM: 6419/1: mmu: Fix MT_MEMORY and MT_MEMORY_NONCACHED pte flags ARM: 6416/1: errata: faulty hazard checking in the Store Buffer may lead to data corruption
| * ARM: relax ioremap prohibition (309caa9) for -final and -stableRussell King2010-10-12
| | | | | | | | | | | | | | ... but produce a big warning about the problem as encouragement for people to fix their drivers. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6Russell King2010-10-12
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| | * cpuimx27: fix i2c bus selectionEric Bénard2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recent clean of i.MX devices registration changed the i2C bus number selected for our platform (Freescale start peripheral ID at 1, kernel now start it at 0 so i.MX27's i2c 1 is kernel's i2c 0). Without this fix, i2c is unusable on this platform. Signed-off-by: Eric Bénard <eric@eukrea.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| | * cpuimx27: fix compile when ULPI is selectedEric Bénard2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | without this patch we get : arch/arm/mach-imx/built-in.o: In function `eukrea_cpuimx27_init': eukrea_mbimx27-baseboard.c:(.init.text+0x44c): undefined reference to `mxc_ulpi_access_ops' Signed-off-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: 6440/1: ep93xx: DMA: fix channel_disableMika Westerberg2010-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When channel_disable() is called, it disables per channel interrupts and waits until channels state becomes STATE_STALL, and then disables the channel. Now, if the DMA transfer is disabled while the channel is in STATE_NEXT we will not wait anything and disable the channel immediately. This seems to cause weird data corruption for example in audio transfers. Fix is to wait while we are in STATE_NEXT or STATE_ON and only then disable the channel. Signed-off-by: Mika Westerberg <mika.westerberg@iki.fi> Acked-by: Ryan Mallon <ryan@bluewatersys.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 6435/1: Fix HWCAP_TLS flag for ARM11MPCore/Cortex-A9Tony Lindgren2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 14eff1812679c76564b775aa95cdd378965f6cfb added proper detection for ARM11MPCore/Cortex-A9 instead of detecting them as ARMv7. However, it was missing the HWCAP_TLS flags. HWCAP_TLS is needed if support for earlier ARMv6 is compiled into the same kernel. Without HWCAP_TLS flags the userspace won't work unless nosmp is specified: Kernel panic - not syncing: Attempted to kill init! CPU0: stopping <c005d5e4>] (unwind_backtrace+0x0/0xec) from [<c004c2f8>] (do_IPI+0xfc/0x184) <c004c2f8>] (do_IPI+0xfc/0x184) from [<c03f25bc>] (__irq_svc+0x9c/0x160) Exception stack(0xc0565f80 to 0xc0565fc8) 5f80: 00000001 c05772a0 00000000 00003a61 c0564000 c05cf500 c003603c c0578600 5fa0: 80033ef0 410fc091 0000001f 00000000 00000000 c0565fc8 c00b91f8 c0057cb4 5fc0: 20000013 ffffffff [<c03f25bc>] (__irq_svc+0x9c/0x160) from [<c0057cb4>] (default_idle+0x30/0x38) [<c0057cb4>] (default_idle+0x30/0x38) from [<c005829c>] (cpu_idle+0x9c/0xf8) [<c005829c>] (cpu_idle+0x9c/0xf8) from [<c0008d48>] (start_kernel+0x2a4/0x300) [<c0008d48>] (start_kernel+0x2a4/0x300) from [<80008084>] (0x80008084) Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 6436/1: AT91: Fix power-saving in idle-mode on 926T processorsAnders Larsen2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Atmel, their 926T processors (AT91 post RM9200) requires 'Wait for Interrupt' mode be entered right after disabling the processor clock in order to minimise current consumption when idle, so do both provided we're not running on a 920T (an RM9200). Furthermore, get rid of the #ifndef CONFIG_DEBUG_KERNEL, since arch_idle() can be turned off completely with the kernel parameter 'nohlt'. Cc: Andrew Victor <avictor.za@gmail.com> Signed-off-by: Anders Larsen <al@alarsen.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: fix section mismatch warnings in Versatile ExpressRussell King2010-10-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | WARNING: vmlinux.o(.text+0xbf30): Section mismatch in reference from the function v2m_timer_init() to the function .init.text:sp804_clocksource_init() The function v2m_timer_init() references the function __init sp804_clocksource_init(). This is often because v2m_timer_init lacks a __init annotation or the annotation of sp804_clocksource_init is wrong. WARNING: vmlinux.o(.text+0xbf3c): Section mismatch in reference from the function v2m_timer_init() to the function .init.text:sp804_clockevents_init() The function v2m_timer_init() references the function __init sp804_clockevents_init(). This is often because v2m_timer_init lacks a __init annotation or the annotation of sp804_clockevents_init is wrong. WARNING: vmlinux.o(.text+0xc524): Section mismatch in reference from the function ct_ca9x4_init() to the function .init.text:l2x0_init() The function ct_ca9x4_init() references the function __init l2x0_init(). This is often because ct_ca9x4_init lacks a __init annotation or the annotation of l2x0_init is wrong. WARNING: vmlinux.o(.text+0xc530): Section mismatch in reference from the function ct_ca9x4_init() to the function .init.text:clkdev_add_table() The function ct_ca9x4_init() references the function __init clkdev_add_table(). This is often because ct_ca9x4_init lacks a __init annotation or the annotation of clkdev_add_table is wrong. WARNING: vmlinux.o(.text+0xc578): Section mismatch in reference from the function ct_ca9x4_init() to the (unknown reference) .init.data:(unknown) The function ct_ca9x4_init() references the (unknown reference) __initdata (unknown). This is often because ct_ca9x4_init lacks a __initdata annotation or the annotation of (unknown) is wrong. Fix these by making ct_ca9x4_init() and v2m_timer_init() both __init. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 6412/1: kprobes-decode: add support for MOVW instructionWill Deacon2010-10-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MOVW instruction moves a 16-bit immediate into the bottom halfword of the destination register. This patch ensures that kprobes leaves the 16-bit immediate intact, rather than assume a 12-bit immediate and mask out the upper 4 bits. Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 6419/1: mmu: Fix MT_MEMORY and MT_MEMORY_NONCACHED pte flagsSantosh Shilimkar2010-10-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit f1a2481c0 sets up the default flags for MT_MEMORY and MT_MEMORY_NONCACHED memory types. L_PTE_USER flag is wrongly set as default for these entries so remove it. Also adding the 'L_PTE_WRITE' flag so that these pages become read-write instead of just being read-only [this stops them being exposed to userspace, which is the main concern here --rmk] Reported-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 6416/1: errata: faulty hazard checking in the Store Buffer may lead to ↵Will Deacon2010-10-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | data corruption On the r2p0, r2p1 and r2p2 versions of the Cortex-A9, data corruption can occur under very rare conditions due to a store buffer optimisation. This workaround sets a bit in the diagnostic register of the Cortex-A9, disabling the optimisation and preventing the problem from occurring. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | Merge branch 'omap-fixes-for-linus' of ↵Linus Torvalds2010-10-13
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 * 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: omap: iommu-load cam register before flushing the entry
| * | | omap: iommu-load cam register before flushing the entryHari Kanigeri2010-10-05
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The flush_iotlb_page is not loading the cam register before flushing the cam entry. This causes wrong entry to be flushed out from the TLB, and if the entry happens to be a locked TLB entry it would lead to MMU faults. The fix is to load the cam register with the address to be flushed before flushing the TLB entry. Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com> Acked-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | | ARM: SAMSUNG: Add a workaround for get_clock() for serial driverMarek Szyprowski2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Serial drivers call get_clock() very early, before platform bus has been set up, this requires a special check to let them get a proper clock. Without this patch, a serial console is broken on S5PV310 and S5PC210 boards. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [kgene.kim@samsung.com: fix coding-style] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Cc: Ben Dooks <ben-linux@fluff.org>
* | | ARM: S5P: Bug fix on errors of build with CONFIG_PREEMPT_NONESeungChull Suh2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds header <linux/sched.h> into the below files for build with CONFIG_PREEMPT_NONE. arch/arm/mach-s5p6440/cpu.c arch/arm/mach-s5p6442/cpu.c arch/arm/mach-s5pc100/cpu.c arch/arm/mach-s5pv210/cpu.c Following is error message of in case of s5pv210_defconfig with CONFIG_PREEMPT_NONE. arch/arm/mach-s5pv210/cpu.c:91: error: implicit declaration of function 'need_resched' Signed-off-by: SeungChull Suh <sc.suh@samsung.com> [kgene.kim@samsung.com: removed mach-s5p64x0/cpu.c] [kgene.kim@samsung.com: added fix mach-s5p6440/cpu.c] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | | ARM: SAMSUNG: Fix build warnings because of unused codesKukjin Kim2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes following unused codes for removing build warnings. arch/arm/plat-samsung/adc.c:438: warning: unused variable 'flags' arch/arm/mach-s5pv210/clock.c:176: warning: 's5pv210_clk_ip4_ctrl' defined but not used Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | | Merge branch 'perf-fixes-for-linus' of ↵Linus Torvalds2010-10-05
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: perf trace scripting: Fix extern struct definitions perf ui hist browser: Fix segfault on 'a' for annotate perf tools: Fix build breakage perf, x86: Handle in flight NMIs on P4 platform oprofile, ARM: Release resources on failure oprofile: Add Support for Intel CPU Family 6 / Model 29
| * | oprofile, ARM: Release resources on failureRobert Richter2010-09-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a resource leak on failure, where the oprofilefs and some counters may not released properly. Signed-off-by: Robert Richter <robert.richter@amd.com> Acked-by: Will Deacon <will.deacon@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: <stable@kernel.org> # .35.x LKML-Reference: <20100929145225.GJ13563@erda.amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | | Merge branch 'omap-fixes-for-linus' of ↵Linus Torvalds2010-10-01
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 * 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: omap: McBSP: tx_irq_completion used in rx_irq_handler omap: Fix compile dependency to LEDS_CLASS
| * | | omap: McBSP: tx_irq_completion used in rx_irq_handlerScott Ellis2010-09-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Looks like a typo from commit d6d834b010. Signed-off-by: Scott Ellis <scott@jumpnowtek.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | omap: Fix compile dependency to LEDS_CLASSTony Lindgren2010-09-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If we LEDS_CLASS is not selected, we will get undefined reference to `led_classdev_register'. Signed-off-by: Tony Lindgren <tony@atomide.com>
* | | | Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2010-09-27
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/home/rmk/linux-2.6-arm: (28 commits) ARM: 6411/1: vexpress: set RAM latencies to 1 cycle for PL310 on ct-ca9x4 tile ARM: 6409/1: davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICE ARM: 6408/1: omap: Map only available sram memory ARM: 6407/1: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entries ARM: pxa: remove pr_<level> uses of KERN_<level> ARM: pxa168fb: clear enable bit when not active ARM: pxa: fix cpu_is_pxa*() not expanding to zero when not configured ARM: pxa168: fix corrected reset vector ARM: pxa: Use PIO for PI2C communication on Palm27x ARM: pxa: Fix Vpac270 gpio_power for MMC ARM: 6401/1: plug a race in the alignment trap handler ARM: 6406/1: at91sam9g45: fix i2c bus speed leds: leds-ns2: fix locking ARM: dove: fix __io() definition to use bus based offset dmaengine: fix interrupt clearing for mv_xor ARM: kirkwood: Unbreak PCIe I/O port ARM: Fix build error when using KCONFIG_CONFIG ARM: 6383/1: Implement phys_mem_access_prot() to avoid attributes aliasing ARM: 6400/1: at91: fix arch_gettimeoffset fallout ARM: 6398/1: add proc info for ARM11MPCore/Cortex-A9 from ARM ...
| * | | | ARM: 6411/1: vexpress: set RAM latencies to 1 cycle for PL310 on ct-ca9x4 tileWill Deacon2010-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PL310 on the ct-ca9x4 tile for the Versatile Express does not need to add additional latency when accessing its cache RAMs. Unfortunately, the boot monitor sets this up for an 8-cycle delay on reads and writes, resulting in greatly reduced memory performance when the L2 cache is enabled. This patch sets the L2 RAM latencies to the correct value of 1 cycle on the ct-ca9x4 tile before enabling the L2 cache. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 6409/1: davinci: map sram using MT_MEMORY_NONCACHED instead of MT_DEVICESantosh Shilimkar2010-09-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Davinci SRAM is mapped as MT_DEVICE becasue of the section mapping pre-requisite instead of intended MT_MEMORY_NONCACHED Since the section mapping limitation gets fixed with first patch in this series, the MT_MEMORY_NONCACHED can be used now. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 6408/1: omap: Map only available sram memorySantosh Shilimkar2010-09-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we map 1 MB section while setting up SRAM on OMAPs Regardless of the actual memory. The physical OCM RAM available on OMAP SOCs is in order of KBs. This patch maps only available sram and cleans up some un-necessary cpu_is_xxx checks. Mapping un-available or non-accessible(secure) memory on the newer ARM processor is dangerous. Because ARM CPUs can now speculatively prefetch, we should avoid mapping any no-existing or secure memory. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 6407/1: mmu: Setup MT_MEMORY and MT_MEMORY_NONCACHED L1 entriesSantosh Shilimkar2010-09-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch populates the L1 entries for MT_MEMORY and MT_MEMORY_NONCACHED types so that at boot-up, we can map memories outside system memory at page level granularity Previously the mapping was limiting to section level, which creates unnecessary additional mapping for which physical memory may not present. On the newer ARM with speculation, this is dangerous and can result in untraceable aborts. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | Merge branch 'fix' of ↵Russell King2010-09-25
| |\ \ \ \ | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6
| | * | | | ARM: pxa: remove pr_<level> uses of KERN_<level>Joe Perches2010-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| | * | | | ARM: pxa: fix cpu_is_pxa*() not expanding to zero when not configuredEric Miao2010-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_PXA3xx is not selected, cpu_is_pxa3xx() doesn't expand to zero, which in some places doesn't result in correct optimization. Signed-off-by: Eric Miao <eric.y.miao@gmail.com> Reported-and-tested-by: Marek Vasut <marek.vasut@gmail.com>
| | * | | | ARM: pxa168: fix corrected reset vectorMark F. Brown2010-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reset vector for pxa168 is 0xffff_0000 not 0x0. This fix allows reboot to work Signed-off-by: Mark F. Brown <mark.brown314@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| | * | | | ARM: pxa: Use PIO for PI2C communication on Palm27xMarek Vasut2010-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Original idea by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
| | * | | | ARM: pxa: Fix Vpac270 gpio_power for MMCMarek Vasut2010-09-24
| | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | GPIO 0 is valid, yet this platform doesn't have any power GPIO for MMC. Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
| * | | | ARM: 6401/1: plug a race in the alignment trap handlerNicolas Pitre2010-09-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the policy for user space is to ignore misaligned accesses from user space, the processor then performs a documented rotation on the accessed data. This is the result of the access being trapped, and the kernel disabling the alignment trap before returning to user space again. In kernel space we always want misaligned accesses to be fixed up. This is enforced by always re-enabling the alignment trap on every entry into kernel space from user space. No such re-enabling is performed when an exception occurs while already in kernel space as the alignment trap is always supposed to be enabled in that case. There is however a small race window when a misaligned access in user space is trapped and the alignment trap disabled, but the CPU didn't return to user space just yet. Any exception would be entered from kernel space at that point and the kernel would then execute with the alignment trap disabled. Thanks to Maxime Bizon <mbizon@freebox.fr> for providing a test module that made this issue reproducible. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 6406/1: at91sam9g45: fix i2c bus speedPeter Korsgaard2010-09-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use a correct udelay value to get bus speed around 100KHz. The udelay value was most likely copied from the older devices, but the 9g45 is signicantly faster (400MHz, DDR, ..), so a udelay of 2 gives a bus speed of around 190KHz, which is too fast for some devices. A udelay value of 5 gives a bus speed of around 90KHz here. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | Merge branch 'for-rmk' of ↵Russell King2010-09-23
| |\ \ \ \ | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/nico/orion
| | * | | | ARM: dove: fix __io() definition to use bus based offsetEric Miao2010-09-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Eric Miao <eric.miao@canonical.com> Acked-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
| | * | | | ARM: kirkwood: Unbreak PCIe I/O portArnaud Patard2010-09-19
| | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The support for the 2 pcie port of the 6282 has broken i/o port by switching *_IO_PHYS_BASE and *_IO_BUS_BASE. In fact, the patches reintroduced the same bug solved by commit 35f029e2514be209eb0e88c7d927f3bcc42a5cc2. So, I'm adding back *_IO_BUS_BASE in resource declaration and fix definition of KIRKWOOD_PCIE1_IO_BUS_BASE. With this change, the xgi card on my t5325 is working again. Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Acked-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net> Cc: stable@kernel.org
| * | | | ARM: Fix build error when using KCONFIG_CONFIGRussell King2010-09-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Jonathan Cameron reports that when using the environment variable KCONFIG_CONFIG, he encounters this error: make[2]: *** No rule to make target `.config', needed by `arch/arm/boot/compressed/vmlinux.lds' Reported-by: Jonathan Cameron <jic23@cam.ac.uk> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 6383/1: Implement phys_mem_access_prot() to avoid attributes aliasingCatalin Marinas2010-09-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv7 onwards requires that there are no aliases to the same physical location using different memory types (i.e. Normal vs Strongly Ordered). Access to SO mappings when the unaligned accesses are handled in hardware is also Unpredictable (pgprot_noncached() mappings in user space). The /dev/mem driver requires uncached mappings with O_SYNC. The patch implements the phys_mem_access_prot() function which generates Strongly Ordered memory attributes if !pfn_valid() (independent of O_SYNC) and Normal Noncacheable (writecombine) if O_SYNC. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 6400/1: at91: fix arch_gettimeoffset falloutPeter Korsgaard2010-09-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5cfc8ee0bb51 (ARM: convert arm to arch_gettimeoffset()) marked all of at91 AND at91x40 as needing ARCH_USES_GETTIMEOFFSET, and hence no high res timer support / accurate clock_gettime() - But only at91x40 needs it. Cc: stable@kernel.org Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com> Acked-by: John Stultz <johnstul@us.ibm.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 6398/1: add proc info for ARM11MPCore/Cortex-A9 from ARMDaniel Walker2010-09-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Setting of these bits can cause issues on other SMP SoC's not produced by ARM. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Daniel Walker <dwalker@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: prevent multiple syscall restartsRussell King2010-09-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Al Viro reports that calling "sys_sigsuspend(-ERESTARTNOHAND, 0, 0)" with two signals coming and being handled in kernel space results in the syscall restart being done twice. Avoid this by clearing the 'why' flag when we call the signal handling code to prevent further syscall restarts after the first. Acked-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr ↵Catalin Marinas2010-09-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | register Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: <stable@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 6389/1: errata: incorrect hazard handling in the SCU may lead to data ↵Will Deacon2010-09-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | corruption On the r2p0, r2p1 and r2p2 versions of the Cortex-A9, data corruption can occur if a shared cache line is replaced on one CPU as another CPU is accessing it. This workaround sets two bits in the diagnostic register of the Cortex-A9, reducing the linefill issuing capabilities of the processor and avoiding the erroneous behaviour. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 06:53:20 -0500