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* OMAP2 clock: drop DELAYED_APP clock flagPaul Walmsley2010-02-24
| | | | | | | | | | | | | | | | All of the clocks that are marked with DELAYED_APP are changed as part of the virt_prcm_set OPP virtual clock. On 24xx, these clocks all need to be changed as part of a group to keep the clock tree functional - hence the need for the VALID_CONFIG bit, which is not present on later OMAPs. These clocks should not be rate-changed independently. So prevent these clocks from being changed independently by dropping their .round_rate and .set_rate function pointers. It then turns out that the DELAYED_APP clock flag is no longer useful, so drop it and the associated code and renumber the clock flags. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Richard Woodruff <r-woodruff2@ti.com>
* OMAP2430 clock: make func_96m_ck parent-selectablePaul Walmsley2010-02-24
| | | | | | | | func_96m_ck was incorrectly marked as being rate-selectable, when in fact it is only parent-selectable. Remove the .set_rate and .round_rate function pointers for this clk. Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own filesPaul Walmsley2010-02-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for multi-OMAP2 kernels, split mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and mach-omap2/clock2430_data.c. 2430 uses a different device space physical memory layout than past or future OMAPs, and we use a different virtual memory layout as well, which causes trouble for architecture-level code/data that tries to support both. We tried using offsets from the virtual base last year, but those patches never made it upstream; so after some discussion with Tony about the best all-around approach, we'll just grit our teeth and duplicate the structures. The maintenance advantages of a single kernel config that can compile and boot on OMAP2, 3, and 4 platforms are simply too compelling. This approach does have some nice benefits beyond multi-OMAP 2 kernel support. The runtime size of OMAP2420-specific and OMAP2430-specific kernels is smaller, since unused clocks for the other OMAP2 chip will no longer be compiled in. (At some point we will mark the clock data __initdata and allocate it during registration, which will eliminate the runtime memory advantage.) It also makes the clock trees slightly easier to read, since 2420-specific and 2430-specific clocks are no longer mixed together. This patch also splits 2430-specific clock code into its own file, mach-omap2/clock2430.c, which is only compiled in for 2430 builds - mostly for organizational clarity. While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was incorrectly marked as being 2420-only, when actually it is present on both OMAP2420 and OMAP2430. Thanks to Tony for some good discussions about how to approach this problem. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Richard Woodruff <r-woodruff2@ti.com>
* OMAP3/4 clock: split into per-chip family filesPaul Walmsley2010-02-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | clock34xx_data.c now contains data for the OMAP34xx family, the OMAP36xx family, and the OMAP3517 family, so rename it to clock3xxx_data.c. Rename clock34xx.c to clock3xxx.c, and move the chip family-specific clock functions to clock34xx.c, clock36xx.c, or clock3517.c, as appropriate. So now "clock3xxx.*" refers to the OMAP3 superset. The main goal here is to prepare to compile chip family-specific clock functions only for kernel builds that target that chip family. To get to that point, we also need to add CONFIG_SOC_* options for those other chip families; that will be done in future patches, planned for 2.6.35. OMAP4 is also affected by this. It duplicated the OMAP3 non-CORE DPLL clkops structure. The OMAP4 variant of this clkops structure has been removed, and since there was nothing else currently in clock44xx.c, it too has been removed -- it can always be added back later when there is some content for it. (The OMAP4 clock autogeneration scripts have been updated accordingly.) Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Ranjith Lohithakshan <ranjithl@ti.com> Cc: Tony Lindgren <tony@atomide.com>
* OMAP clock: drop .id field; ensure each clock has a unique namePaul Walmsley2010-02-24
| | | | | | | | After the clkdev conversion, the struct clk.id field became superfluous, so, drop it. Bring the clock names closer to the TRMs and ensure they are unique for debugfs. Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP clock: compress clock flags down to a u8Paul Walmsley2010-02-24
| | | | | | | | There are now only eight OMAP clock flags, so renumber the flags to fit in a u8 and shrink the size of struct clk.flags from a u32 to a u8. The intention is to save memory. Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP2 clock: drop CONFIG_PARTICIPANT clock flagPaul Walmsley2010-02-24
| | | | | | | | | | | | | | | | | It turns out that the only purpose of the CONFIG_PARTICIPANT clock flag is to prevent omap2_clk_set_rate() and omap2_clk_set_parent() from being executed on clocks with that flag set. The rate-changing component can be more directly accomplished by dropping the .set_rate and .round_rate function pointers from those CONFIG_PARTICIPANT struct clks. As far as the parent-changing component is concerned, it turns out that none of the CONFIG_PARTICIPANT clocks have multiple parent choices, so all that is necessary is for omap2_clk_set_parent() to bail out early if the new parent is equal to the old parent. Implement this change and get rid of the flag, which has always had a confusing name (it appears to be a Kconfig option, falsely). Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Richard Woodruff <r-woodruff2@ti.com>
* OMAP2xxx clock: drop DELAYED_APP flag from non-clksel clocksPaul Walmsley2010-02-24
| | | | | | | | | The DELAYED_APP flag is effective only with clksel clocks, so drop it from clocks that are not rate-changeable or that use non-clksel rate changing code (e.g., virt_prcm_set). Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Richard Woodruff <r-woodruff2@ti.com>
* OMAP2xxx clock: GFX functional clock rates are not independently changeablePaul Walmsley2010-02-24
| | | | | | | | | | According to the OMAP242x TRM Rev X Figure 5-15 "Clock Output Control - Functional Clocks 2", the GFX functional clocks should be marked both DELAYED_APP and CONFIG_PARTICIPANT, meaning that their rates must be reprogrammed as part of a larger OPP set change. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Richard Woodruff <r-woodruff2@ti.com>
* OMAP4 clock: drop the CLOCK_IN_OMAP4430 clock flagPaul Walmsley2010-02-24
| | | | | | | | | | | The CLOCK_IN_OMAP4430 clock flag is not currently needed in the OMAP4 ES1 clock tree, and platform discrimination via clock flags is deprecated in favor of the clkdev mechanism, so, drop it. (The OMAP4 clock tree autogeneration script has been updated accordingly.) Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com>
* OMAP2/3/4 clock: fix DPLL multiplier value errors; also copyrights, ↵Paul Walmsley2010-02-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | includes, documentation The maximum DPLL multiplier (M) values for OMAP2xxx and OMAP3xxx are one increment higher than they should be. See for example the OMAP242x TRM Rev X Section 5.10.6 "Clock Generator Registers" and the OMAP36xx TRM Rev C Table 3-202 "CM_CLKSEL1_PLL". Programming a 0 into the DPLL's M register bitfield is valid for OMAP2/3 and indicates that the DPLL should enter MN-bypass mode. Also, increase the minimum multiplier (M) value for the DPLL rate rounding code from 1 to 2, to ensure that it does not inadvertently put the DPLL into bypass. Note that the register documentation in the OMAP2xxx and OMAP3xxx TRMs does not make clear that the actual DPLL divider value (the "N") is the content of the appropriate register bitfield for the N value, _plus one_. (In other words, an N register bitfield of 0 indicates a DPLL divider value of 1.) This is only clearly documented in the OMAP4430 TRM, in, for example, OMAP4430 TRM Rev A Table 3-1167 "CM_CLKSEL_DPLL_USB". While here, update copyrights, add kerneldoc for struct dpll_data, drop the unused struct dpll_data.max_tolerance field, remove some unnecessary #includes in DPLL-related code, and replace the #include of <linux/module.h> with <linux/list.h>, which is what was really needed. The OMAP4 clock autogenerator script has been updated accordingly. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com>
* OMAP3 clock: add support for 192Mhz DPLL4M2 outputVishwanath BS2010-02-24
| | | | | | | | | | | | | | | In 3630, DPLL4M2 output can be 96MHz or 192MHz (for SGX to run at 192). This patch has changes to support this feature. 96MHz clock is generated by dividing 192Mhz clock by 2 using CM_CLKSEL_CORE register. SGX can select Core Clock, 192MHz clock or CM_96M_FCLK as it's functional clock. In summary changes done are: 1. Added a feature called omap3_has_192mhz_clk and enabled for 3630 2. Added a new clock node called omap_192m_alwon_ck 3. Made omap_96m_alwon_fck to derive its clock from omap_192m_alwon_ck Signed-off-by: Vishwanath BS <Vishwanath.bs@ti.com> [paul@pwsan.com: fixed whitespace] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3 clock: Introduce 3630 DPLL4 HSDivider changesVishwanath BS2010-02-24
| | | | | | | | | | | | Divider (M2, M3, M4, M5 and M6) field width has been increased by 1 bit in 3630. This patch has changes to accommodate this in CM dynamically based on chip version. Basically new clock nodes have been added for 3630 DPLL4 M2,M3,M4,M5 and M6 and value of these nodes are used if cpu type is 3630. Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com> [paul@pwsan.com: updated to apply on 2.6.34 queue; comments added] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3 clock: introduce DPLL4 JtypeRichard Woodruff2010-02-24
| | | | | | | | | | | | | | | | DPLL4 for 3630 introduces a changed block called j type dpll, requiring special divisor bits and additional reg fields. To allow for silicons to use this, this is introduced as a flag and is enabled for 3630 silicon. OMAP4 also has j type dpll for usb. Tested with 3630 ZOOM3 and OMAP3430 ZOOM2 Signed-off-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Vishwanath BS <Vishwanath.bs@ti.com> [paul@pwsan.com: added some comments; updated copyrights and credits; fixed some style issues] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* ARM: OMAP4 clock domain: Add check for avoiding dependency related update.Abhijit Pagare2010-02-24
| | | | | | | | | A check is added for avoiding the sleep/wakeup dependency updates for OMAP4 as the structures for the dependencies are currently absent. Signed-off-by: Abhijit Pagare <abhijitpagare@ti.com> [paul@pwsan.com: added warnings, explanatory comment, copyright update] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3630: Clock: Workaround for DPLL HS divider limitationMike Turquette2010-02-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements a workaround for the DPLL HS divider limitation in OMAP3630 as given by Errata ID: i556. Errata: When PWRDN bit is set, it resets the internal HSDIVIDER divide-by value (Mx). The reset value gets loaded instead of the previous value. The following HSDIVIDERs exhibit above behavior: . DPLL4 : M6 / M5 / M4 / M3 / M2 (CM_CLKEN_PLL[31:26] register bits) . DPLL3 : M3 (CM_CLKEN_PLL[12] register bit). Work Around: It is mandatory to apply the following sequence to ensure the write value will be loaded in DPLL HSDIVIDER FSM: The global sequence when using PWRDN bit is the following: . Disable Mx HSDIVIDER clock output related functional clock enable bits (in CM_FCLKEN_xxx / CM_ICLKEN_xxx) . Enable PWRDN bit of HSDIVIDER . Disable PWRDN bit of HSDIVIDER . Read current HSDIVIDER register value . Write different value in HSDIVIDER register . Write expected value in HSDIVIDER register . Enable Mx HSDIVIDER clock output related functional clocks (CM_FCLKEN_xxx / CM_ICLKEN_xxx) Signed-off-by: Mike Turquette <mturquette@ti.com> Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Vijaykumar GN <vijaykumar.gn@ti.com> [paul@pwsan.com: updated patch to apply; made workaround function static; marked as being 36xx-specific] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP: HWMOD: Add support for early device register into omap device layerThara Gopinath2010-02-24
| | | | | | | | | | | | | This patch adds support in omap device layer to register devices as early platform devices. Certain devices needed during system boot up like timers, gpio etc can be registered as early devices. This will allow for them to be probed very early on during system boot up. This patch adds a parameter is_early_device in omap_device_build. Depending on this parameter a call to early_platform_add_devices or platform_register_device is made. Signed-off-by: Thara Gopinath <thara@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3: hwmod: support to specify the offset position of various SYSCONFIG ↵Thara Gopinath2010-02-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | register bits. In OMAP3 Some modules like Smartreflex do not have the regular sysconfig register.Instead clockactivity bits are part of another register at a different bit position than the usual bit positions 8 and 9. In OMAP4, a new scheme is available due to the new protocol between the PRCM and the IPs. Depending of the scheme, the SYSCONFIG bitfields position will be different. The IP_REVISION register should be at offset 0x00. It should contain a SCHEME field. From this we can determine whether the IP follows legacy scheme or the new scheme. 31:30 SCHEME Used to distinguish between old scheme and current. Read 0x0: Legacy protocol. Read 0x1: New PRCM protocol defined for new OMAP4 IPs For legacy IP 13:12 MIDLEMODE 11:8 CLOCKACTIVITY 6 EMUSOFT 5 EMUFREE 4:3 SIDLEMODE 2 ENAWAKEUP 1 SOFTRESET 0 AUTOIDLE For new OMAP4 IP's, the bit position in SYSCONFIG is (for simple target): 5:4 STANDBYMODE (Ex MIDLEMODE) 3:2 IDLEMODE (Ex SIDLEMODE) 1 FREEEMU (Ex EMUFREE) 0 SOFTRESET Unfortunately In OMAP4 also some IPs will not follow any of these two schemes. This is the case at least for McASP, SmartReflex and some security IPs. This patch introduces a new field sysc_fields in omap_hwmod_sysconfig which can be used by the hwmod structures to specify the offsets for the sysconfig register of the IP.Also two static structures omap_hwmod_sysc_type1 and omap_hwmod_sysc_type2 are defined which can be used directly to populate the sysc_fields if the IP follows legacy or new OMAP4 scheme. If the IP follows none of these two schemes a new omap_hwmod_sysc_fields structure has to be defined and passed as part of omap_hwmod_sysconfig. Signed-off-by: Thara Gopinath <thara@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3 clock: Remove FreqSel for 3630Vishwanath BS2010-02-24
| | | | | | | | | | DPLL_FREQSEL field in CLKEN_PLL register is no longer valid for OMAP3630. So remove references to that. Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com> Cc: Sergei Shtylyov <sshtylyov@mvista.com> [paul@pwsan.com: added comment fix from Sergei Shtylyov] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP2/3: PRCM: fix misc. compiler warningsKevin Hilman2010-02-24
| | | | | | | | - missing return in omap_prcm_get_reset_sources() - potential use of uninitialized variable in omap_prcm_arch_reset() Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3 clock: Check return values for clk_get()Sanjeev Premi2010-02-24
| | | | | | | | | | | This patch checks if clk_get() returned success for the clocks used in function omap2_clk_arch_init(). This version incorporates review comments from Kevin Hilman and Paul Walmsley. Signed-off-by: Sanjeev Premi <premi@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* AM35xx: Add clock support for new modules on AM35xxRanjith Lohithakshan2010-02-24
| | | | | | | | | | | | This patch adds clock support for the following AM35xx modules - Ethernet MAC - CAN Controller (HECC) - New MUSB OTG Controller with integrated Phy - Video Processing Front End (VPFE) - Additional UART (UART4) Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP2/3 clock: Extend find_idlest() to pass back idle state valueRanjith Lohithakshan2010-02-24
| | | | | | | | | | | | | | | | Current implementation defines clock idle state indicators based on the cpu information (cpu_is_omap24xx() or cpu_is_omap34xx()) in a system wide manner. This patch extends the find_idlest() function in clkops to pass back the idle state indicator for that clock, thus allowing idle state indicators to be defined on a per clock basis if required. This is specifically needed on AM35xx devices as the new IPSS clocks indicates the idle status (0 is idle, 1 is ready) in a way just opposite to how its handled in OMAP3 (0 is ready, 1 is idle). Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com> [paul@pwsan.com: updated to apply after commit 98c45457 et seq.] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3 PM: Adding counters for power domain logic off and mem off during ↵Thara Gopinath2010-02-24
| | | | | | | | | | | | | | | | | | | | | | retention. This patch adds counters to keep track of whether the powerdomain logic or software controllable memory banks are turned off when the power domain enters retention. During power domain retention if logic gets turned off, the scenario is known as Open Switch Retention. Also during retention s/w controllable memory banks of a power domain can be chosen to be kept in retention or off. This patch adds one counter per powerdomain to track the power domain logic state during retention. Number of memory bank state counters added depends on the number of software controllable memory banks of the powerdomain. To view these counters do cat ../debug/pm_debug/count Signed-off-by: Thara Gopinath <thara@ti.com> [paul@pwsan.com: conditional expressions simplified; counter increment code moved to its own function] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3 PM: Defining .pwrsts_logic_ret field for core power domain structureThara Gopinath2010-02-24
| | | | | | | | | This patch adds the flag .pwrsts_logic_ret info for the core power domain in the associated powerdomain structure. This flag specifies the states core domain logic can hit in event of the domain entering retention. Signed-off-by: Thara Gopinath <thara@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP2/3 PM: Adding powerdomain APIs for reading the next logic and mem stateThara Gopinath2010-02-24
| | | | | | | | | | | This patch adds APIs pwrdm_read_logic_retst and pwrdm_read_mem_retst for reading the next programmed logic and memory state a powerdomain is to hit in event of the next power domain state being retention. These are needed for OSWR support. Signed-off-by: Thara Gopinath <thara@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3: Clock: Added IDLEST definitions for SGXTero Kristo2010-02-24
| | | | | | | | Added definitions for OMAP3430ES2_ST_SGX_SHIFT and OMAP3430ES2_ST_SGX_MASK as these were missing. Signed-off-by: Tero Kristo <tero.kristo@nokia.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP3: clock: use std _MASK suffix for CM_FCLKEN_IVA2 definesKevin Hilman2010-02-24
| | | | | | | | Add _MASK suffix to CM_FCLKEN_IVA2 bitfieds to conform with the rest of the usage in cm-regbits-34xx.h of using _SHIFT and _MASK suffixes. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP: omap_device: when 'called from invalid state', print stateKevin Hilman2010-02-24
| | | | | | | | | | | | | | The omap_device_[enable|idle|shutdown] functions print a warning when called from an invalid state. Print the invalid state in the warning messages. This also uses __func__ to get the function name. Also, move the entire print string onto a single line to facilitate grepping or error messages. Recent discussions on LKML show strong preference for grep-able code vs. strict 80 column limit. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP: omap_device: add omap_device_is_valid()Kevin Hilman2010-02-24
| | | | | | | | | | | | | | | | | | The omap_device struct contains a 'struct platform_device'. Normally, converting a platform_device pointer to an omap_device pointer consists of simply doing a container_of(), as is done currently by the to_omap_device() macro. However, if this is attempted when using platform_device that has not been created as part of the omap_device creation, the container_of() will point to a memory location before the platform_device pointer which will contain random data. Therefore, we need a way to detect valid omap_device pointers. This patch solves this by using the simple magic number approach. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* Merge branch 'omap-fixes-for-linus' into omap-for-linusTony Lindgren2010-02-17
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| * omap: Remove DEBUG_FS dependency for mux name checkingRanjith Lohithakshan2010-02-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The check for a valid mux name should be performed regardless of whether DEBUG_FS is enabled or not. Otherwise without DEBUG_FS, we get: Unable to handle kernel NULL pointer dereference at virtual address 00000000 pgd = c0004000 [00000000] *pgd=00000000 Internal error: Oops: 5 [#1] last sysfs file: Modules linked in: CPU: 0 Not tainted (2.6.33-rc8 #10) PC is at strcmp+0x18/0x40 LR is at omap_mux_init_signal+0x68/0x14c ... This fixes the issue currently seen with boards not booting up if DEBUG_FS is not enabled in defconfig. Note that the earlier ifndef + ifdef now becomes simpler ifdef else: If CONFIG_OMAP_MUX is selected, we use pin names. If it's not selected, we only want the GPIO to mux register mapping. Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | OMAP4: MCPDM: Register McPDM platform deviceJorge Eduardo Candelaria2010-02-15
| | | | | | | | | | | | | | | | Add platform device for McPDM interface in OMAP4 and register its memory and irq resources. Signed-off-by: Jorge Eduardo Candelaria <x0107209@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | ARM: OMAP4: Add McPDM base addressJorge Eduardo Candelaria2010-02-15
| | | | | | | | | | | | | | Define McPDM physical and L3 base address for OMAP4 Signed-off-by: Jorge Eduardo Candelaria <x0107209@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | OMAP4: IRQ: Add McPDM IRQ definitionJorge Eduardo Candelaria2010-02-15
| | | | | | | | | | | | | | Support for McPDM IRQs in OMAP4 Signed-off-by: Jorge Eduardo Candelaria <x0107209@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | arm: omap: kill compile warning on board-4430-sdp.cFelipe Balbi2010-02-15
| | | | | | | | | | | | | | sdp4430_uart_config isn't used anywhere, so remove it. Signed-off-by: Felipe Balbi <felipe.balbi@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | AM35xx: Update irq.h for AM35xx IPSS module interruptsVaibhav Hiremath2010-02-15
| | | | | | | | | | Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | AM35xx: Add AM35xx intr_clr & sw_rst cntrl reg bit definitionVaibhav Hiremath2010-02-15
| | | | | | | | | | | | | | | | | | | | | | AM3517/05 has few additional control module registers to control the new IP's, like VPFE, USBOTG, CPGMAC. This patch adds the bit defination for INTR_CLR and SW_RST control register. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | AM35xx: Introduce am35xx.h fileVaibhav Hiremath2010-02-15
| | | | | | | | | | | | | | | | | | | | | | | | Add base address definations for new AM35xx IPSS modules, like VPFE, USBOTG, CPGMAC. Please note that the OMAP34xx IVA2 memory space is being used for AM35xx IPSS modules. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Sriramakrishnan <srk@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | omap3: pm: Add T2 Keypad as a wakeup sourceLesly A M2010-02-15
| | | | | | | | | | | | | | | | | | Changes for setting the padconf value for sys_nirq line which is connected to T2 INTR1. This will fix the T2 keypad wakeup. Signed-off-by: Lesly A M <x0080970@ti.com> Signed-off-by: Teerth Reddy <teerth@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | omap3: Clean-up for omap_mux_initTony Lindgren2010-02-15
| | | | | | | | | | | | | | Get rid of the ifdeffery in omap_mux_init by creating omap_mux_init_package and omap_mux_init_signals functions. Signed-off-by: Tony Lindgren <tony@atomide.com>
* | omap_hsmmc: Allow for a shared VccQAdrian Hunter2010-02-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EMMC can have two voltage supplies, Vcc and VccQ which are implemented in the code as consumer supplies vmmc and vmmc_aux. If the regulator that supplies vmmc_aux is shared with other consumers, then sending it to sleep will disrupt those consumers. However, the TWL4030-family regulators may have OFF remapped to SLEEP, in which case 'regulator_disable()' will put the regulator to sleep only when all consumers are disabled - which is the desired behaviour. This patch adds a platform data field to allow that option. Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | omap_hsmmc: Allow for power saving without going offAdrian Hunter2010-02-15
| | | | | | | | | | | | | | | | | | An eMMC may be always powered on, so that the lowest power saving state possible is sleeping. Add a field to the platform data to indicate that. Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | omap: RX51: Remux to pull eMMC lines down when powering offAdrian Hunter2010-02-15
| | | | | | | | | | | | | | | | | | | | | | It has been discovered that, when eMMC is powered off, current will flow from OMAP eMMC data pull-ups to the eMMC voltage supply. Configuring pads for OMAP off-mode does not help because eMMC is powered off independently of OMAP off-mode. Hence the pads are now re-configured when eMMC is powered on or off. Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | omap: Reconnect hsmmc context loss countAdrian Hunter2010-02-15
| | | | | | | | | | | | | | | | Call the PM context-loss count function, now that there is a prototype for it. Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | omap: Rename hsmmc symbols to reflect independence from twl4030Adrian Hunter2010-02-15
| | | | | | | | | | | | | | | | hsmmc.[ch] no longer has any dependency on twl4030 and variable names should be renamed to reflect that. Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | omap: Rename mmc-twl4030 files to hsmmcAdrian Hunter2010-02-15
| | | | | | | | | | | | | | | | mmc-twl4030.[ch] no longer has any dependency on twl4030 and should be renamed to reflect that. Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | omap_hsmmc: Move gpio and regulator control from board fileAdrian Hunter2010-02-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the setup code for GPIO's and Voltage Regulators from the board file mmc-twl4030.c to the driver omap_hsmmc.c. PBIAS and other system control configuration remains in the board file. Moving GPIO code to the driver makes the board initialisation code independent of when GPIO's are defined. That makes the board initialisation now entirely independent of its original twl4030 roots. Moving Voltage Regulator code to the driver allows for further development of regulator support in the core MMC code. It also permits the MMC core to be compiled as a module, because the board code no longer calls MMC core functions. Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | omap3: Add support for flash on 3430SDP boardVimal Singh2010-02-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for flashes on 3430SDP boards. All three NAND, NOR and OneNAND are supported. I have tested it on 3430SDP (ES2 and ES3.1). This patch can be treated as an example to "how to utilize": 'gpmc-nand.c' and 'board-sdp-flash.c'. Similar patches can be created for 2430sdp and 3630sdp or any other similar board. Signed-off-by: Vimal Singh <vimalsingh@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | omap3: SDP: Introducing 'board-sdp-flash.c' for flash initVimal Singh2010-02-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds 'board-sdp-flash.c', which could be utilized by boards similar to 3430SDP. (For ex: 2430sdp, 36030sdp). This file does initialization for all three flash devices present in SDP boards (NOR, NAND, OneNAND), by finding there 'cs' number dynamically using switch setting information (S8: 1-4). This also expects partition information from core board files (for ex: board-3430sdp.c). Which allows to choose different default partitions for different boards. A new structure is created for this purpose: 'flash_partitions' in 'mach/board-sdp.h'. This has two members: 1. struct mtd_partition *parts 2. int nr_parts A board file is expected to fill this structure and pass it to 'sdp-flsash-init'. Partition information should be passed in structure array of 'flash_partitions'. Partition information should be passed in below sequence in array: NOR OneNAND NAND Signed-off-by: Vimal Singh <vimalsingh@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 02:10:47 -0500